Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
View Patent ↗Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement The present invention provides a method for connecting an integrated circuit (C 1 ), in particular a chip or a wafer or a hybrid, to a substrate (C 2 ), which has the following steps: provision of a first electrical contact structure (KF 1 , BP, LB; KF 1 , BP′) on a first main area (HF 1 ) of the integrated circuit (C 1 ); provision of a corresponding second electrical contact structure (KF 2 ) on a second main area (HF 2 ) of the substrate (C 2 ); at least one of the contact structures, the first electrical contact structure (KF 1 , BP, LB; KF 1 , BP′) or the second electrical contact structure (KF 2 ), being elastic; placement of the first electrical contact structure (KF 1 , BP, LB; KF 1 , BP′) onto the corresponding second electrical contact structure (KF 2 ), so that both are in electrical contact and under mechanical compression pressure (P); and connection of a region of the main area (HF 1 ) surrounding the first electrical contact structure (KF 1 , BP, LB; KF 1 , BP′) to a corresponding region surrounding the second electrical contact structure (KF 2 ) of the second main area (HF 2 ) by an adhesive layer (KS), so that the first electrical contact structure (KF 1 , BP, LB; KF 1 , BP′) and/or the second electrical contact structure (KF 2 ) are compressed in the connected state. The invention likewise provides a corresponding circuit arrangement.
1. Method for connecting an integrated circuit, in particular a chip or a wafer or a hybrid, to a substrate, which has the following steps:
(a) providing of a first electrical contact structure on a first main area of the integrated circuit;
(b) providing of a corresponding second electrical contact structure on a second main area of the substrate;
(c) at least one of the contact structures, the first electrical contact structure or the second electrical contact structure, being elastic;
(d) placing of the first electrical contact structure onto the corresponding second electrical contact structure, so that both are in electrical contact and under mechanical compression pressure; and
(e) connecting of a region of the main area surrounding the first electrical contact structure to a corresponding region surrounding the second electrical contact structure of the second main area by an adhesive layer, so that the first electrical contact structure and/or the second electrical contact structure are compressed in the connected state; a region of the adhesive layer is recessed in a region around the elastic one of the first contact structure and the second contact structure such that spacing is provided between the adhesive layer and the elastic one of the first contact structure and the second contact structure.
2. Method according to claim 1 , wherein the first electrical contact structure has a contact area on the first main area of the integrated circuit, a nonconducting elastic elevation and an interconnect connecting the upper side of the nonconducting elastic elevation to the contact area.
3. Method according to claim 1 , wherein the first electrical contact structure has a contact area on the first main area of the integrated circuit and a conducting elastic elevation.
4. Method according to claim 1 , wherein the region of the main area surrounding the first electrical contact structure is covered by a covering layer and the adhesive layer is provided on the covering layer.
5. Method according to claim 4 , wherein the covering layer partly overlaps the contact area on the first main area of the integrated circuit in its periphery.
6. Method according to claim 1 , wherein the substrate is a further integrated circuit, in particular a chip or a wafer or a hybrid.
7. Method according to claim 6 , wherein the region of the main area surrounding the second electrical contact structure is covered by a further covering layer and the adhesive layer is provided on the further covering layer.
8. Method according to claim 7 , wherein the second electrical contact structure has a further contact area and the further covering layer partly overlaps the further contact area on the second main area of the substrate in its periphery.
9. Method according to claim 1 , wherein the first electrical contact structure and the corresponding electrical contact area are connected to each other, preferably by soldering or conductive adhesive bonding.
10. Method according to claim 1 , wherein the adhesive layer has such an elasticity that, when there is different thermal expansion of the substrate and the integrated circuit, it makes it possible for them to be displaced with respect to each other in the common plane of the first and second main areas.