IP Library Granted Patent US 7,053,681
Granted Patent B2
US 7,053,681 · App. 10/863,516 · Granted May 30, 2006

Comparator and method for amplifying an input signal

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Quick Facts
Patent No.
US 7,053,681
App. No.
10/863,516
Granted
May 30, 2006
Kind
B2
Abstract

The invention is aimed at providing a novel semi-conductor component, as well as a novel process for reading test data. There is a process for reading test data is made available, including reading test data generated during a semi-conductor component test procedure from at least one test data register of a semi-conductor component, storing the test data in at least one useful data memory cell provided on the semi-conductor component, and reading the test data from the at least one useful data memory cell.

Claims (27)

1. A method for amplifying an input signal, comprising:

providing, by use of a first current source/sink, a first current to an output node;

sinking, by use of a third current source/sink, a third current from the output node; and

inputting the input signal to a control input of the third current source/sink,

wherein a control input of the first current source/sink is connected to the third current source/sink, and to a clamping capacitor, such that an output node load capacitance, representing a second current source/sink, is rapidly charged when the input signal changes its state in a first direction, and is rapidly discharged when the input signal changes its state in a second direction, wherein

when the node load capacitance is rapidly charged, an output signal changes its state in a first direction, and, when the node load capacitance is rapidly discharged, the output signal changes its state in the second direction,

the clamping capacitor is coupled to a resistor,

providing, by use of a fourth current source/sink, a fourth current to the output node,

a signal derived from the input signal is input to a control input of the fourth current source/sink, and

when the input signal changes are relatively small, and/or relatively large and below a reference voltage, the changes in the current provided by the fourth current source/sink prevent the output signal from changing its state.

2. A comparator, comprising:

a first current source/sink, coupled to an output node; and

a third current source/sink, coupled to the output node, wherein a control input of the third current source/sink is coupled to a signal input line, and

a control input of the first current source/sink is connected to the third current source/sink and a clamping capacitor, such that an output node load capacitance, representing a second current source/sink, is rapidly charged when a signal at the signal input line changes its state in a first direction, and is rapidly discharged when the signal at the signal input line changes its state in a second direction, wherein

the control input of the first current source/sink is additionally connected to a feed forward capacitor.

3. The comparator of claim 2 , wherein the clamping capacitor is coupled to a resistor.

4. The comparator of claim 2 , wherein the output node is coupled to an inverter.

5. The comparator of claim 2 , further comprising a fourth current source/sink.

6. The comparator of claim 5 , wherein the fourth current source/sink is coupled to the output node.

7. The comparator of claim 5 , wherein the fourth current source/sink via a resistor is coupled to the signal input line.

8. The comparator of claim 5 , wherein the resistor is coupled to a capacitor.

9. A method for amplifying an input signal, comprising:

providing, by use of a first current source/sink, a first current to an output node;

sinking, by use of a third current source/sink, a third current from the output node; and

inputting the input signal to a control input of the third current source/sink,

wherein a control input of the first current source/sink is connected to the third current source/sink, at a clamping capacitor and additionally by the input via a feed forward capacitor, such that an output node load capacitance, representing a second current source/sink, is rapidly charged when the input signal changes its state in a first direction, and is rapidly discharged when the input signal changes its state in a second direction.

10. The method of claim 9 , wherein the input signal is additionally input to a control input of the first current source/sink.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036888/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2004
From: ACHARYA, PRAMOD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015889/0848 →