Method for improving the read signal in a memory having passive memory elements

1. A method for improving read signals in a memory comprising passive memory elements provided at crossover locations of word and bit lines, and in which stored digital information is represented by a respective resistance of the memory elements, the method comprising:

determining logic levels of information bits to be written to the memory elements associated with a respective bit line;

inverting the logic levels of the information bits if more than half of information bits to be written to the memory elements associated with the respective bit line have a logic level corresponding to a low-value resistance of the memory elements;

writing the information bits to the memory elements; and

generating an additional check bit, a logic level of which represents an inverted or non-inverted state of the information bits.

2. The method as claimed in claim 1 , wherein information bits stored in an inverted state are inverted back to a non-inverted state when the information bits are to be read from the memory.

3. The method as claimed in claim 1 , wherein the low-value resistance of the memory elements corresponds to logic level “0” and the high-value resistance corresponds to logic level “1”.

4. The method as claimed in claim 1 , wherein, in the event of writing information with a number of information bits identical to the number of memory elements on a respective bit line, the method further comprises:

determining separately the respective number of the information bits having a logic level corresponding to a high-value or the low-value resistance of the memory elements;

setting a check bit with the logic level corresponding to the inverted or non-inverted logic level of the information bits; and

feeding the information bits sequentially into the memory elements of the respective bit lines.

5. The method as claimed in claim 1 , wherein the number of information bits having a logic level corresponding to the high-value or the low-value resistance of the memory elements is determined by counting.

6. The method as claimed in claim 5 , wherein half of the information bits corresponding to the number of memory elements on the respective bit line are counted.

7. The method as claimed in claim 4 , wherein the number of information bits having a logic level corresponding to the high-value or low-value resistance of the memory elements is determined by analog weighting.

8. The method as claimed in claim 7 , wherein the information bits are weighted by comparing their logic level with a reference voltage.

9. The method as claimed in claim 2 , wherein the check bit is read out prior to the information bits.

10. The method as claimed in claim 1 , wherein in the event of writing information with a number of information bits that is smaller than the number of memory elements on the respective bit line, the method further comprises:

dividing the memory elements into groups in which the number of memory elements is equal to the number of information bits;

assigning each group of memory elements a check bit memory element;

writing the information bits to a group of memory elements in the inverted or non-inverted state; and

writing information bits having the logic level corresponding to the high-value resistance to remaining groups of the memory elements.

11. The method as claimed in claim 1 , wherein, for random writing of information to an individual memory element on a bit line, the method further comprises:

reading all the memory elements or a group of memory elements on the bit line;

generating an associated check bit from the memory elements read; and

writing the information to the memory element with the generated check bit.