Method for fabricating a semiconductor structure
View Patent ↗The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate ( 1 ) made of silicon with a first hard mask layer ( 10; 10′ ) made of silicon oxide and an overlying second hard mask layer ( 15; 15′ ) made of silicon; providing a masking layer ( 30; 30′ ) made of silicon oxide above and laterally with respect to the second hard mask layer ( 15; 15′ ) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate ( 1 ); providing a photoresist mask ( 25 ) above the masking layer ( 30; 30′ ) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate ( 1 ); opening the masking layer ( 30; 30′ ) in a first plasma process using the photoresist mask ( 25 ), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer ( 10; 10′ ) and second hard mask layer ( 15; 15′ ) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate ( 1 ) in a fourth plasma process using the opened first hard mask layer ( 10; 10′ ); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.
1. Method for fabricating a semiconductor structure having the steps of:
providing a semiconductor substrate ( 1 ) made of silicon with a first hard mask layer ( 10 ; 10 ′) made of silicon oxide and an overlying second hard mask layer ( 15 ; 15 ′) made of silicon;
providing a masking layer ( 30 ; 30 ′) made of silicon oxide above and laterally with respect to the second hard mask layer ( 15 ; 15 ′) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate ( 1 );
providing a photoresist mask ( 25 ) above the masking layer ( 30 ; 30 ′) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate ( 1 );
opening the masking layer ( 30 ; 30 ′) in a first plasma process using the photoresist mask ( 25 ), the edge region (RB) being covered by a shielding device (AR);
opening the first hard mask layer ( 10 ; 10 ′) and second hard mask layer ( 15 ; 15 ′) in a second and third plasma process; and
forming the trenches (DT) in the semiconductor substrate ( 1 ) in a fourth plasma process using the opened first hard mask layer ( 10 ; 10 ′);
the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.
2. Method according to claim 1 ,
characterized
in that the masking layer ( 30 ) made of silicon oxide is provided by a deposition process.
3. Method according to claim 1 ,
characterized
in that the masking layer ( 30 ) made of silicon oxide is provided by a thermal oxidation process.
4. Method according to claim 1 ,
characterized
in that the second hard mask layer ( 15 ) is provided such that it is made of polysilicon.
5. Method according to claim 1 ,
characterized
in that the second hard mask layer ( 15 ′) is provided such that it is made of amorphous silicon.
6. Method according to claim 1 ,
characterized
in that a silicon nitride layer ( 5 ) is provided between the semiconductor substrate ( 1 ) and the first hard mask layer ( 10 ; 10 ′) and is opened by a fifth plasma process using the opened first hard mask layer ( 10 ; 10 ′).
7. Method according to claim 1 ,
characterized
in that the first plasma process is highly selective with respect to silicon.
8. Method according to claim 1 ,
characterized
in that the first hard mask layer ( 10 ; 10 ′) is fabricated from silane oxide.