Semiconductor memory device
View Patent ↗The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or data clock terminal; at least one test circuit, a respective test circuit being assigned to an input receiver and the test circuit being designed for determining at least one predetermined property of the assigned input receiver.
1. A semiconductor device, comprising:
a plurality of receiver circuits for receiving a data signal presented on a data pin when the device is in a normal operating mode, wherein each receiver circuit comprises an input receiver;
a plurality of test circuits including the receiver circuits, wherein only one separate test circuit is assigned to each of the receiver circuits, wherein each test circuit further includes a buffer, wherein each test circuit is configured to couple a respective one of its buffers with a respective one of its input receivers to form a respective ring oscillator in a test mode, wherein a frequency of an oscillating signal generated from the respective ring oscillator is determined by the input receiver of the receiver circuit to which the test circuit is assigned; and
a measurement pin for reading out a measurement signal indicative of the frequency of a respective oscillating signal.
2. The semiconductor device of claim 1 , wherein the frequency of the oscillating signal is indicative of a propagation delay of a respective receiver circuit.
3. The semiconductor device of claim 1 , further comprising:
one or more data pins for receiving the data signal; and
a pin for receiving a reference voltage to be applied to an input of a respective test circuit.
4. The semiconductor device of claim 3 , wherein the pin for receiving the reference voltage is one of the data pins.
5. The semiconductor device of claim 1 , wherein the plurality of test circuits each comprise a comparator circuit configured to generate a binary measurement signal indicative of the frequency of the respective oscillating signal relative to a reference frequency.
6. A semiconductor device, comprising:
a data pin;
a plurality of receiver circuits for receiving a data signal presented on the data pin when the device is in a normal operating mode, wherein each receiver circuit comprises an input receiver;
a plurality of test circuits including the receiver circuits, wherein only one separate test circuit is assigned to each of the receiver circuits, wherein each test circuit further includes a buffer, wherein each test circuit is configured to couple a respective one of its buffers with a respective one of its input receivers to form a respective ring oscillator in a test mode, wherein a reference voltage is applied to an input of each of the test circuits when the device is in the test mode, and wherein a frequency of an oscillating signal generated from the respective ring oscillator is determined by the input receiver of the receiver circuit to which the test circuit is assigned; and
a measurement pin for reading out a measurement signal indicative of the frequency of a respective oscillating signal.
7. The semiconductor device of claim 6 , wherein the plurality of test circuits each comprise a voltage divider that divides the reference voltage to generate a voltage signal applied to an inverting input of a receiver circuit.
8. The semiconductor device of claim 7 , wherein a ratio of resistances of the voltage divider is variable based on an output voltage of the respective receiver circuit.
9. A semiconductor device, comprising:
a data pin;
a plurality of receiver circuits for receiving a data signal presented on the data pin when the device is in a normal operating mode, wherein each receiver circuit comprises an input receiver;
a plurality of test circuits including the receiver circuits, wherein only one separate test circuit is assigned to each of the receiver circuits, wherein each test circuit further includes a buffer, wherein each test circuit is configured to couple a respective one of its buffers with a respective one of its input receivers to form a respective ring oscillator in a test mode, wherein a frequency of an oscillating signal generated from the respective ring oscillator is determined by the input receiver of the receiver circuit to which the test circuit is assigned;
a frequency divider circuit that generates a measurement signal indicative of the frequency of a respective oscillating signal by dividing a frequency of the respective oscillating signal by a predetermined factor; and
a measurement pin for reading out the measurement signal.
10. A method for testing a plurality of receiver circuits of a memory device, comprising:
placing the device in a test mode, thereby causing a plurality of test circuits, including the receiver circuits as components, to form a respective ring oscillator for each of the plurality of test circuits, wherein only one separate test circuit is assigned to each of the receiver circuits, wherein each test circuit further includes a buffer, wherein each test circuit is configured to couple a respective one of its buffers with a respective one of its input receivers to form the respective ring oscillator in the test mode, wherein a frequency of an oscillating signal generated from the respective ring oscillator is determined by the input receiver of the receiver circuit to which the test circuit is assigned; and
monitoring a measurement signal provided on a pin of the memory device to determine the property of each of the receiver circuits, wherein the measurement signal is indicative of the frequency of a respective oscillating signal.
11. The method of claim 10 , wherein monitoring the measurement signal comprises monitoring the measurement signal to determine when the measurement signal stops oscillating.
12. The method of claim 10 , wherein monitoring the measurement signal comprises monitoring the measurement signal to determine an asymmetry of the oscillating signal based on a frequency of the measurement signal.
13. The method of claim 10 , wherein monitoring the measurement signal comprises monitoring the measurement signal to determine one of a duration of a low output signal of a respective receiver circuit and a duration for a high output signal.
14. The method of claim 10 , further comprising providing a reference voltage on an external pin of the memory device, wherein the reference voltage is used by the plurality of test circuits to generate the oscillating signal.
15. A semiconductor device, comprising:
a plurality of receiver circuits, wherein each receiver circuit comprises an input receiver;
test means for generating an oscillating signal, wherein the test means comprises only one separate test circuit for each of the plurality of receiver circuits, wherein each test circuit further includes a buffer, wherein each test circuit is configured to couple a respective one of its buffers with a respective one of its input receivers to form a respective ring oscillator in a test mode, wherein a frequency of the oscillating signal generated from the respective ring oscillator is determined by the input receiver of a respective receiver circuit; and
readout means for monitoring a measurement signal indicative of the frequency of a respective oscillating signal.
16. The semiconductor device of claim 15 , wherein the test means comprises a single test circuit for the plurality of the one or more receiver circuits.
17. The semiconductor device of claim 15 , wherein the readout means comprises an external pin of the memory device.