Integrated circuit including memory cell for storing an information item and method

1. An integrated circuit comprising:

a memory element comprising:

a programmable metallization cell (PMC) resistance component having a solid electrolyte material, wherein the solid electrolyte material is selectably configurable into a first state having a high electrical resistance and into a second state having a low electrical resistance;

a resistance element connected to the PMC resistance component in such a way as to reduce the total resistance of the memory element in the first state; and

wherein the resistance element is connected in parallel with the PMC resistance component.

2. The integrated circuit of claim 1 , wherein an electrical resistance of the resistance element is greater than a resistance value of the PMC resistance component in the second state.

3. The integrated circuit of claim 1 , wherein the memory element is arranged on a substrate and further comprises a first electrode and a second electrode, wherein the solid electrolyte material and the resistance element are arranged between the first electrode and the second electrode.

4. The integrated circuit of claim 3 , wherein the first electrode is arranged on the substrate, wherein an insulator region is arranged on the first electrode, wherein the second electrode is arranged on the insulator region, wherein the insulator region has a passage opening, wherein the resistance element is arranged at least partly on an inner wall of the passage opening, and wherein the solid electrolyte material is provided in the passage opening and arranged in electrical connection between the first electrode and the second electrode.

5. The integrated circuit of claim 4 , wherein the resistance element comprises doped silicon.

6. The integrated circuit of claim 4 , wherein the resistance element comprises doped titanium nitride.

7. The integrated circuit comprising:

a memory element comprising:

a programmable metallization cell (PMC) resistance component having a solid electrolyte material, wherein the solid electrolyte material is selectably configurable into a first state having a high electrical resistance and into a second state having a low electrical resistance;

a resistance element connected to the PMC resistance component in such a way as to reduce the total resistance of the memory element in the first state; and

wherein an electrical resistance of the resistance element is less than a resistance value of the PMC resistance component in the first state.

8. A memory circuit, comprising:

a memory cell for storing an information item comprising a memory element, the memory element comprising:

a programmable metallization cell (PMC) resistance component having a solid electrolyte material, wherein the solid electrolyte material is selectably configurable into a first state having a high electrical resistance and into a second state having a low electrical resistance; and

a resistance element connected to the PMC resistance component in such a way as to reduce the total resistance of the memory element in the first state; and

a read-out circuit coupled to the memory cell to detect a state of the solid electrolyte material, the read-out circuit comprising a differential amplifier and a feedback resistor connected between an input and an output of the differential amplifier.

9. The memory circuit of claim 8 , wherein the feedback resistor has a resistance set correspondingly to a resistance of the memory element.

10. The memory circuit of claim 8 , wherein the resistance element is connected in parallel with the PMC resistance component.

11. The memory circuit of claim 10 , wherein an electrical resistance of the resistance element is less than a first resistance value of the PMC resistance component in the first state and greater than a second resistance value of the PMC resistance component in the second state.

12. The memory circuit of claim 11 , wherein the memory element is arranged on a substrate and further comprises a first electrode and a second electrode, wherein the solid electrolyte material and the resistance element are arranged between the first electrode and the second electrode.

13. The memory circuit of claim 12 , wherein the first electrode is arranged on the substrate, wherein an insulator region is arranged on the first electrode, wherein the second electrode is arranged on the insulator region, wherein the insulator region has a passage opening, wherein the resistance element is arranged at least partly on an inner wall of the passage opening, and wherein the solid electrolyte material is provided in the passage opening and arranged in electrical connection between the first electrode and the second electrode.

14. The memory circuit of claim 13 , wherein the resistance element comprises one of doped silicon and doped titanium nitride.

15. The memory circuit of claim 8 , wherein the memory cell further comprises a switch connected between the memory element and a bit line which is connected to the read-out circuit, the switch operatively connected to a word line and controlled by a signal on the word line.

16. A method for producing a memory cell having a memory element, the method comprising:

arranging a first electrode on a substrate;

arranging an insulation layer over the first electrode;

forming a passage opening in the insulation layer which uncovers a portion of the first electrode;

arranging a resistance material at least on an inner wall of the passage opening to form a resistance region;

arranging a solid electrolyte material into the passage opening to form a programmable resistance region; and

arranging a second electrode on the resistance material and the solid electrolyte material,

whereby a programmable metallization cell (PMC) resistance component and a resistance element of the memory element are formed, and

wherein the resistance region extends from the first electrode to the second electrode.

17. The method of claim 16 , wherein the passage opening is formed utilizing an anisotropic etching method.

18. The method of claim 16 , wherein the resistance material is arranged on the inner wall of the passage opening utilizing ion implantation into the insulation layer.

19. The method of claim 18 , wherein the resistance material is formed in a remaining portion of the passage opening.