Test circuitry wafer
View Patent ↗Method and apparatus for testing a plurality of devices on a device wafer. One embodiment provides a test circuitry wafer having a first surface and a second surface, the test circuitry wafer comprising a plurality of contact pads disposed on the first surface for contacting a plurality of device pads on the device wafer, a plurality of interface pads disposed on the second surface for contacting probe needles on a probe card and one or more test features disposed in the test circuitry wafer, wherein the one or more test features are electrically connected to at least one of the contact pads and the interface pads.
1. An apparatus for testing a device wafer having a plurality of devices formed thereon, comprising:
a test circuitry wafer having a first surface and a second surface, the test circuitry wafer comprising:
a plurality of contact pads disposed on the first surface for contacting a plurality of device pads on the device wafer;
a plurality of interface pads disposed on the second surface for contacting probe needles on a probe card; and
one or more test features disposed in the test circuitry wafer, wherein the one or more test features comprise one or more circuit components electrically connected to at least one of the contact pads and the interface pads, and wherein the one or more test features comprise a plurality of design-for-test (DFT) circuit blocks connected for testing the plurality of devices.
2. The apparatus of claim 1 , wherein the plurality of DFT circuit blocks corresponds in number to the devices formed on the device wafer.
3. The apparatus of claim 1 , wherein the plurality of interface pads are disposed in a relaxed-pitch arrangement as compared to the plurality of contact pads.
4. The apparatus of claim 3 , wherein the test circuitry wafer further comprises a plurality of pitch-relaxing connectors electrically connected to the plurality of contact pads.
5. The apparatus of claim 4 , wherein the plurality of contact pads are disposed at a first pitch corresponding to a device-pad pitch on the device wafer.
6. The apparatus of claim 3 , further comprising:
the probe card having probe needles, wherein the probe needles are disposed in the same relaxed-pitch arrangement corresponding to the plurality of interface pads.
7. The apparatus of claim 1 , further comprising:
an interface wafer connected between the test circuitry wafer and the device wafer.
8. The apparatus of claim 7 , further comprising:
a carrier for transporting the test circuitry wafer and the interface wafer with the device wafer, wherein the carrier includes one or more alignment posts for aligning the interface wafer on the device wafer and one or more clamps for securing the test circuitry wafer on the device wafer.
9. The apparatus of claim 1 , further comprising:
a tester connected to the probe card for controlling test operations.
10. The apparatus of claim 1 , further comprising:
a carrier for transporting the test circuitry wafer with the device wafer.
11. A method for testing a device wafer having a plurality of devices formed thereon, comprising:
positioning a test circuitry wafer on the device wafer, the test circuitry wafer comprising:
a plurality of contact pads disposed on a first surface for contacting a plurality of device pads on the device wafer;
a plurality of interface pads disposed on a second surface for contacting probe needles on a probe card; and
one or more test features disposed in the test circuitry wafer, wherein the one or more test features comprise one or more circuit components electrically connected to at least one of the contact pads and the interface pads, and wherein the one or more test features comprise a plurality of design-for-test (DFT) circuit blocks connected for testing the plurality of devices;
connecting the probe card having a plurality of probe needles to the test circuitry wafer;
connecting a tester to the probe card; and
performing one or more test operations on one or more devices on the device wafer.
12. The method of claim 11 , further comprising:
aligning and securing the test circuitry wafer onto the device wafer in a carrier having one or more alignment posts for aligning the test circuitry wafer on the device wafer and one or more clamps for securing the test circuitry wafer on the device wafer.
13. The method of claim 11 , further comprising:
connecting an interface wafer between the test circuitry wafer and the device wafer.
14. The method of claim 11 , wherein the plurality of devices are tested at the same time.
15. An apparatus for testing a device wafer, comprising:
a test circuitry wafer having a first surface and a second surface, the test circuitry wafer comprising:
a plurality of contact means disposed on the first surface for contacting a plurality of device pads on the device wafer;
a plurality of interface means disposed on the second surface for contacting probe needles on a probe card; and
one or more test feature means disposed in the test circuitry wafer, wherein the one or more test feature means comprise one or more circuit components electrically connected to at least one of the contact means and the interface means, and wherein the one or more test features comprise a plurality of design-for-test (DFT) circuit blocks connected for testing devices on the device wafer.
16. The apparatus of claim 15 , wherein the plurality of DFT circuit blocks corresponds in number to the devices formed on the device wafer.
17. The apparatus of claim 15 , wherein the test circuitry wafer further comprises a plurality of pitch-relaxing means for electrically connected to the plurality of contact pads.
18. The apparatus of claim 15 , further comprising:
an interface wafer connected between the test circuitry wafer and the device wafer.