Test device for wafer testing digital semiconductor circuits
View Patent ↗The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.
1. A test device for testing digital semiconductor circuits at wafer level, comprising:
an interposer comprising a printed circuit board with contact pins on both sides;
a needle or contact stud card; and
a probe card which sends and receives digital test signals to and from a test head and distributes signal channels, carrying test signals, to respective locations on a wafer via the interposer;
wherein:
the interposer is arranged between the needle or contact stud card and the probe card so as to mechanically and thermally decouple an interface of the probe card with the test head and needles or contact studs disposed on the needle or contact stud card;
all signal channels in the test device or signal channels which carry time-critical test signals in the test device comprise a respective logic signal amplifier mounted on the printed circuit board of the interposer; and
each logic signal amplifier amplifies a respective signal received from the wafer or transmitted to the wafer using high and low signal levels.
2. The test device according to claim 1 , wherein logic signal amplifiers in the signal channels are logic buffers.
3. The test device according to claim 1 , wherein the logic signal amplifiers in the signal channels are in physical proximity to the needle or contact stud card.
4. The test device according to claim 1 , wherein at least one of the logic signal amplifiers amplifies a respective signal received from the wafer or transmitted to the wafer using stipulated high and low levels.
5. The test device according to claim 1 , wherein at least one of the logic signal amplifiers amplifies a respective signal received from the wafer or transmitted to the wafer using variable high and/or low signal levels.
6. The test device according to claim 5 , wherein the variable signal levels can each be set or regulated from outside of the interposer.
7. The test device according to claim 1 , wherein the interposer is configured to be retrofit with the test device.
8. The test device according to claim 5 , wherein at least one of the logic signal amplifiers comprises first and second MOS transfer gates connected in parallel, and wherein the first MOS transfer gate is supplied with a high level and the second MOS transfer gate is supplied with a low level and inputs of the first and second MOS transfer gates are respectively supplied with complementary input signals.