Fabrication method for a semiconductor structure and corresponding semiconductor structure
View Patent ↗The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate ( 1 ) with a gate dielectric ( 5 ); provision of a plurality of multilayered, elongate gate stacks (GS 1; GS 2 ) which essentially run parallel to one another on the gate dielectric ( 5 ), which gate stacks have a bottommost layer ( 10 ) made of silicon; provision of a first liner layer ( 60 ) made of a first material over the gate stacks (GS 1; GS 2 ) and the gate dielectric ( 5 ) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer ( 10 ) made of silicon; provision of sidewall spacers ( 70 ) made of a second material on the vertical sidewalls of the gate stacks (GS 1; GS 2 ) over the first liner layer ( 60 ), a region of the first liner layer ( 60 ) over the gate dielectric ( 5 ) between the gate stacks (GS 1; GS 2 ) remaining free; selective removal of the first liner layer ( 60 ) with respect to the sidewall spacers ( 70 ) for the purpose of laterally uncovering the bottommost layer ( 10 ) made of silicon of the gate stacks (GS 1; GS 2 ); and selective oxidation of the uncovered bottommost layer ( 10 ) for the purpose of forming sidewall oxide regions ( 50 ′) on the gate stacks (GS 1; GS 2 ).
1. Fabrication method for a semiconductor structure having the following steps:
a) providing of a semiconductor substrate with a gate dielectric;
b) providing of a plurality of multilayered, elongate gate stacks which essentially run parallel to one another on the gate dielectric, which gate stacks have a bottommost layer made of silicon;
c) providing of a first liner layer made of a first material over the gate stacks and the gate dielectric uncovered beside the latter, the thickness of which liner layer is less than a thickness of the bottommost layer made of silicon;
d) providing of sidewall spacers made of a second material on the vertical sidewalls of the gate stacks over the first liner layer, a region of the first liner layer over the gate dielectric between the gate stacks remaining free;
e) removing selectively of the first liner layer with respect to the sidewall spacers and the gate dielectric for the purpose of laterally uncovering the bottommost layer made of silicon of the gate stacks; and
f) oxidizing selectively of the uncovered bottommost layer for the purpose of forming sidewall oxide regions on the gate stacks.
2. Method according to claim 1 , wherein, after the selective oxidation, a third liner layer made of the first or second material is provided over the gate stacks and the gate dielectric uncovered beside the latter.
3. Method according to claim 1 , wherein the second material is silicon oxide or doped polysilicon.
4. Method according to claim 1 , wherein the gate stacks have a second from bottom layer made of WN, a third from bottom layer made of W and a topmost layer made of silicon nitride.
5. Method according to claim 1 , wherein the first material is silicon nitride.
6. Method according to claim 1 , wherein selective removal is effected by means of a wet etching.
7. Method according to claim 4 , wherein the sidewall oxide regions on the gate stacks are not in contact with the second from bottom layer made of WN.