Input return path based on V
View Patent ↗Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return path noise may be decoupled from the power for receiver circuits, for example, by utilizing separate power supply lines, such as V DDQ and V SSQ , as input signal return path.
1. A method for reducing jitter of an input signal applied to an input node of a receiver circuit via an input signal line, comprising:
coupling power supply nodes of the receiver circuit to first power supply lines;
providing a return path for the input signal via second power supply lines, decoupled from the first power supply lines, wherein the second power supply lines are coupled to the input signal line via capacitance between a package pin and the input node of the receiver circuit;
coupling electro-static discharge (ESD) circuitry, placed inline with the input signal line, with the second power supply voltage lines; and
coupling a voltage reference line, for carrying a reference voltage signal used by the receiver circuit in determining a logic level of the input signal, to the first power supply voltage lines.
2. An input circuit configuration, comprising:
a receiver circuit coupled to first power supply lines for power;
an input signal line for carrying an input signal to the receiver circuit;
a return path for the input signal through input capacitance associated with the input signal line, and one or more second power supply lines, decoupled from the first power supply lines;
electro-static discharge (ESD) circuitry in line with the input signal line; and
further comprising a voltage reference line for carrying a reference voltage signal used by the receiver circuit in determining a logic level of the input signal, wherein capacitance associated with the voltage reference line is coupled to the first power supply lines for power.
3. The input circuit configuration of claim 2 , wherein the ESD circuitry is coupled to the second power supply lines for power.
4. An integrated circuit (IC) device, comprising:
first power supply lines;
one or more second power supply lines;
one or more package pins for receiving input signals supplied to the device;
receiver circuits coupled to the first power supply lines for power;
input signal lines for carrying the input signals to input nodes of the receiver circuits;
one or more common return paths for the input signals provided through input capacitance between the package pins and input nodes of the receiver circuits and the second power supply lines;
electro-static discharge (ESD) circuitry in line with the input signal lines, wherein the ESD circuitry is coupled to the second power supply lines for power; and
further comprising a voltage reference line for carrying a reference voltage signal used by the receiver circuit in determining a logic level of the input signal, wherein capacitance associated with the voltage reference line is coupled to the first power supply lines for power.
5. The IC device of claim 4 , further comprising output circuitry for driving output signals, wherein the output circuitry is coupled to the second power supply lines for power.
6. A dynamic random access memory (DRAM) device comprising:
one or more memory cell arrays;
one or more package pins for receiving data signals supplied to the device, the data signals carrying information to be written to the memory cell arrays;
first power supply lines;
one or more second power supply lines;
receiver circuits coupled to the first power supply lines for power;
data signal lines for carrying the data signals from the package pins to input nodes of the receiver circuits;
one or more common return paths for the data signals provided through input capacitance between the package pins and input nodes of the receiver circuits and the second power supply lines;
electro-static discharge (ESD) circuitry in line with the data signal lines, wherein the ESD circuitry is coupled to the second power supply lines for power; and
a voltage reference line for carrying a reference voltage signal used by the receiver circuits in determining logic levels of the data signals, wherein capacitance associated with the voltage reference line is coupled to the first power supply lines for power.
7. The DRAM device of claim 6 , further comprising output circuitry for driving output signals multiplexed onto the package pins, wherein the output circuitry is coupled to the second power supply lines for power.
8. A method for reducing utter of an input signal applied to an input node of a receiver circuit via an input signal line, comprising:
coupling power supply nodes of the receiver circuit to first power supply lines;
providing a return path for the input signal via second power supply lines, decoupled from the first power supply lines, wherein the second power supply lines are coupled to the input signal line via capacitance between a package pin and the input node of the receiver circuit;
coupling electro-static discharge (ESD) circuitry, placed inline with the input signal line, with the second power supply voltage lines; and
coupling a voltage reference line, for carrying a reference voltage signal used by the receiver circuit in determining a logic level of the input signal, to the second power supply voltage lines.
9. A dynamic random access memory (DRAM) device comprising:
one or more memory cell arrays;
one or more package pins for receiving data signals supplied to the device, the data signals carrying information to be written to the memory cell arrays;
first power supply lines;
one or more second power supply lines;
receiver circuits coupled to the first power supply lines for power;
data signal lines for carrying the data signals from the package pins to input nodes of the receiver circuits;
one or more common return paths for the data signals provided through input capacitance between the package pins and input nodes of the receiver circuits and the second power supply lines;
electro-static discharge (ESD) circuitry in line with the data signal lines, wherein the ESD circuitry is coupled to the second power supply lines for power; and
a voltage reference line for carrying a reference voltage signal used by the receiver circuits in determining logic levels of the data signals, wherein capacitance associated with the voltage reference line is coupled to the second power supply lines for power.
10. The DRAM device of claim 9 , further comprising output circuitry for driving output signals multiplexed onto the package pins, wherein the output circuitry is coupled to the second power supply lines for power.