Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips
View Patent ↗In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.
1. A method for monitoring layout changes for semiconductor chips, the method comprising:
generating a first group of error data by comparing a first layout with wiring and layout rules;
generating a second group of error data by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout;
performing a comparison between the first group of error data and the second group of error data; and
outputting for evaluation only error data that are different in the first and second groups.
2. The method as claimed in claim 1 , wherein performing a comparison comprises exclusive-ORing the first and second groups of error data.
3. The method as claimed in claim 1 , wherein performing a comparison comprises performing a digital data comparison of the first and second groups of error data.
4. The method as claimed in claim 1 , wherein performing a comparison comprises performing an optical comparison.
5. The method as claimed in claim 1 , wherein generating the first group of error data further comprises storing the first group of error data in a GDS format and wherein generating the second group of error data further comprises storing the second group of error data in the GDS format.
6. A method of making a semiconductor device, the method comprising:
providing a first layout;
generating a first group of error data by comparing the first layout with wiring and layout rules;
generating a second layout from the first layout;
generating a second group of error data by comparing the second layout with the wiring and layout rules;
performing a comparison between the first group of error data and the second group of error data;
outputting only error data that are different in the first and second groups;
generating a final layout based at least in part on the outputted error data; and
fabricating a semiconductor device based upon the final layout.
7. The method as claimed in claim 6 , wherein performing a comparison comprises exclusive-ORing the first and second groups of error data.
8. The method as claimed in claim 6 , wherein performing a comparison comprises performing a digital data comparison of the first and second groups of error data.
9. The method as claimed in claim 8 , wherein performing a comparison comprises performing a comparison using a processor.
10. The method as claimed in claim 6 , wherein performing a comparison comprises performing an optical comparison.
11. The method as claimed in claim 10 , wherein performing a comparison comprises performing a manual optical comparison.
12. The method as claimed in claim 10 , wherein performing a comparison comprises performing an optical comparison using image processing software.
13. The method as claimed in claim 6 , wherein generating the first group of error data further comprises storing the first group of error data in a GDS format and wherein generating the second group of error data further comprises storing the second group of error data in the GDS format.
14. The method as claimed in claim 6 , wherein fabricating a semiconductor device comprises forming metal interconnect lines that electrically couple active elements on a semiconductor substrate.
15. The method as claimed in claim 14 , wherein forming metal interconnect lines comprises forming copper interconnect lines using a damascene process.