Fabricating a memory cell array
View Patent ↗A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.
1. An integrated circuit that comprises a memory cell array, the memory cell array comprising:
a plurality of memory cells that are at least partially formed in a semiconductor substrate, each of the memory cells comprising a storage capacitor, a select transistor including a channel region and a gate electrode, wherein the gate electrode surrounds at least two sides of the channel region, each select transistor including first and second source/drain regions that are oriented such that a flow of current through each channel region includes a portion that is substantially horizontal with respect to a top surface of the semiconductor substrate; and
a plurality of word lines, the word lines being connected to the gate electrodes;
wherein, in a cross section of the memory cell array through each channel region, a bottom edge of the gate electrode surrounding at least two sides of the channel region is disposed at a distance from the top surface of the semiconductor substrate that is different in relation to a distance of the bottom edges of the word lines from the top surface of the semiconductor substrate.
2. An integrated circuit comprising a memory cell array, the memory cell array comprising:
a plurality of memory cells that are at least partially formed in a semiconductor substrate, each of the memory cells comprising a storage capacitor, a select transistor including a channel region and a gate electrode, wherein the gate electrode surrounds at least two sides of the channel region, each select transistor including first and second source/drain regions that are oriented such that a flow of current through each channel region includes a portion that is substantially horizontal with respect to a top surface of the semiconductor substrate; and
a plurality of word lines, the word lines being connected to the gate electrodes;
wherein, in a cross section of the memory cell array through each channel region, a bottom edge of the gate electrode surrounding at least two sides of the channel region is disposed at a distance from a top surface of the semiconductor substrate that is different in relation to a distance of the bottom edges of the word lines from the top surface of the semiconductor substrate.
3. The integrated circuit of claim 2 , wherein the memory cells are arranged in cell rows and cell columns, the storage capacitors and select transistors are arranged in a checkerboard pattem, each select transistor being assigned to a respective diagonally adjacent first field and each storage capacitor being assigned to a respective intervening and diagonally adjacent second field.
4. The integrated circuit of claim 2 , wherein the memory cells are arranged in cell rows and cell columns, and each storage capacitor is arranged in an adjacent pair with a corresponding select transistor such that at least two adjacent memory cells are assigned to a common bit line contact.
5. The integrated circuit of claim 2 , wherein at least one storage capacitor comprises a trench capacitor formed in a trench within the substrate.
6. The integrated circuit of claim 2 , wherein at least one storage capacitor comprises a stacked capacitor.
7. The integrated circuit of claim 2 , wherein a second capacitor electrode of the storage capacitor is connected to a first source/drain region of the select transistor for each memory cell via a connecting region disposed within the semiconductor substrate.
8. The integrated circuit of claim 2 , wherein a second capacitor electrode of the storage capacitor is connected to a first source/drain region of the select transistor for each memory cell via a connecting region disposed above the top surface of the semiconductor substrate.
9. The integrated circuit of claim 2 , wherein each gate electrode is substantially U-shaped in cross-section and suffounds three sides of the corresponding conductive channel region.
10. The integrated circuit of claim 2 , wherein each gate electrode comprises polysilicon.
11. The integrated circuit of claim 2 , wherein each wordline comprises one of tungsten and tungsten silicide.
12. An integrated circuit comprising a memory cell array, the memory cell array comprising:
a plurality of memory cells that are at least partially formed in a semiconductor substrate, each memory cell including a gate electrode and a select transistor that includes a channel region and first and second source/drain regions that are oriented such that a flow of current through each channel region includes a portion that is substantially horizontal with respect to a top surface of the semiconductor substrate, wherein the gate electrode is at least partially disposed within the semiconductor substrate; and
a plurality of wordlines that are connected to the gate electrodes, wherein a bottom edge of each of the gate electrodes is disposed at a distance from a top surface of the semiconductor substrate that is different in relation to a distance of the bottom edges of the word lines from the top surface of the semiconductor substrate.
13. The integrated circuit of claim 12 , wherein the wordlines comprise an electrically conductive material that is different from an electrically conductive material of the gate electrodes.
14. The integrated circuit of claim 12 , wherein each memory cell includes a select transistor including a channel region, and the gate electrode has a substantially U-shaped cross-section and is oriented to surround three sides of the corresponding channel region.
15. The integrated circuit of claim 12 , wherein each gate electrode comprises polysilicon.
16. The integrated circuit of claim 12 , wherein each wordline comprises one of tungsten and tungsten silicide.
17. An integrated circuit comprising a memory cell array, the memory cell array comprising:
a plurality of memory cells that are at least partially formed in a semiconductor substrate, each of the memory cells comprising a transistor including a gate electrode and first and second source/drain regions, wherein the first and second source/drain regions are disposed adjacent a top surface of the semiconductor substrate and are oriented such that a flow of current through a channel region includes a portion that is substantially horizontal with respect to the top surface of the semiconductor substrate, and the gate electrode is at least partially disposed within the semiconductor substrate; and
a plurality of wordlines that are connected to the gate electrodes;
wherein, in a cross section through at least one channel region of the memory cell array, a bottom edge of each gate electrode is disposed at a distance from a top surface of the semiconductor substrate that is different in relation to a distance of the bottom edges of the word lines from the top surface of the semiconductor substrate.
18. The integrated circuit of claim 17 , wherein the word lines comprise an electrically conductive material that is different from an electric ally conductive material of the gate electrodes.
19. The integrated circuit of claim 17 , wherein each gate electrode is substantially U-shaped in cross-section and surrounds three sides of a corresponding channel region.
20. The integrated circuit of claim 17 , wherein the at least one channel region is arranged in a fin-like semiconductor substrate region.
21. The memory cell array integrated circuit of claim 17 , wherein each gate electrode comprises polysilicon.
22. The integrated circuit of claim 17 , wherein each wordline comprises one of tungsten and tungsten silicide.
23. The integrated circuit of claim 2 , wherein the word lines comprise an electrically conductive material that is different from an electrically conductive material of the gate electrodes.