Integrated memory arrangement based on resistive memory cells and production method

1. An integrated memory arrangement comprising:

a plurality of resistive memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having a first capacitance; and

an electrical additional capacitance associated with each memory cell that increases the capacitance of the memory cell.

2. The memory arrangement of claim 1 , comprising wherein the additional capacitance includes a capacitor connected in parallel with the memory cell.

3. The memory arrangement of claim 1 , comprising wherein the additional capacitance includes a contact capacitance formed in a contact adjacent to the memory cell.

4. The memory arrangement of claim 1 , comprising wherein the additional capacitance integrated directly into the memory cell.

5. The memory arrangement of claim 1 , comprising wherein the memory arrangement is a CBRAM, in which the resistive memory cells are in each case conductive bridging junction contact junctions.

6. The memory arrangement of claim 1 , comprising wherein the memory arrangement is a PCRAM, in which the memory cells have an active layer made of a material with a changeable phase state.

7. The memory arrangement of claim 1 , comprising wherein it is an MRAM.

8. The memory arrangement of claim 4 , comprising wherein the additional capacitance is implemented in the memory cell by increasing an electrode area of the memory cell.

9. The integrated memory arrangement as claimed in claim 4 , wherein the additional capacitance is implemented in the memory cell by reducing its electrode spacing.

10. The memory arrangement of claim 4 , wherein the additional capacitance is implemented by increasing a dielectric constant of an active layer lying between the electrodes of the memory cell.

11. The memory arrangement of claim 4 , comprising wherein part of a cross section of the memory cell is filled by a dielectric having a higher dielectric constant than a dielectric constant of an active layer between the electrodes.

12. A method for producing an integrated memory arrangement comprising:

forming a plurality of resistive memory cells having a cell capacitance; and

increasing the cell capacitance of the resistive memory cells, including integrating an electrical additional capacitance with respect to each memory cell.

13. The method of claim 12 , comprising:

forming the additional capacitance by connecting a capacitor in parallel with the memory cell.

14. The method of claim 12 , comprising:

forming the additional capacitance by a contact capacitance in a contact adjacent to the memory cell.

15. The method of claim 12 , comprising:

integrating the additional capacitance directly into the memory cell.

16. The method of claim 12 , comprising:

using the method to produce a CBRAM with CBJ memory cells.

17. The method of claim 12 , comprising:

using the method for producing a PCRAM memory.

18. The method of claim 12 , comprising:

using the method for producing an MRAM memory.

19. The method of claim 15 , comprising:

implementing the additional capacitance by increasing the electrode area in the memory cell.

20. The method of claim 15 , comprising:

implementing the additional capacitance by reducing the electrode spacing in the memory.

21. The method of claim 15 , comprising:

implementing the additional capacitance by increasing the dielectric constant of an active layer lying between the electrodes of the memory cell.

22. The method of claim 15 , comprising:

forming the additional capacitance by filling part of a cross section of the memory cell with a dielectric having a higher dielectric constant than that of an active layer lying between the electrodes of the memory cell.

23. An integrated memory arrangement comprising:

a plurality of resistive memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having a first capacitance; and

means for providing an electrical additional capacitance associated with each memory cell that increases the capacitance of the memory cell.

24. The memory arrangement of claim 23 , comprising wherein the means for providing an additional capacitance includes a capacitor connected in parallel with the memory cell.

25. A random access memory cell comprising:

a top electrode;

a bottom electrode;

an insulator layer positioned between the top electrode and the bottom electrode;

an active region formed in the insulator layer;

a dielectric region having very high dielectric constant is formed in the insulator layer, between the top electrode and the bottom electrode; providing an additional capacitor to the memory cell and increasing the capacitance of the memory cell.

26. The memory cell of claim 25 , comprising:

wherein the dielectric region is made of a high-k material.

27. The memory cell of claim 26 , wherein the active region is made of a chalcogenide material.