Trench and a trench capacitor and method for forming the same

1. A method of fabricating an integrated circuit, the method comprising:

etching a trench into a surface of a semiconductor substrate, wherein a trench wall is exposed;

forming at least one layer on the trench wall, wherein a topmost layer comprises a sealing layer made of a sealing material;

performing a selective epitaxy method in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate;

etching a partial trench in a surface of the epitaxially grown semiconductor layer overlying the trench, wherein at least part of the sealing layer is uncovered; and

removing the uncovered part of the sealing layer,

wherein the trench and the partial trench form an unfilled stack trench.

2. The method as claimed in claim 1 , wherein the selective epitaxy method is performed in such a way that no semiconductor material grows directly on the sealing layer.

3. A method of fabricating an integrated circuit, the method comprising:

etching a trench into a surface of a semiconductor substrate, wherein a trench wall is exposed;

forming at least one layer on the trench wall, wherein a topmost layer comprises a sealing layer made of a sealing material;

performing a selective epitaxy method in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate;

etching a partial trench in a surface of the epitaxially grown semiconductor layer, wherein at least part of the sealing layer is uncovered;

removing the uncovered part of the sealing layer:

forming at least one layer on a trench wall of the partial trench, wherein a topmost layer comprises a second sealing layer made of a sealing material;

performing a selective epitaxy method in such a way that a second monocrystalline semiconductor layer is formed on the surface of the first monocrystalline semiconductor layer;

etching a second partial trench in a surface of the second monocrystalline semiconductor layer such that at least part of the second sealing layer is uncovered; and

removing the uncovered part of the second sealing layer.

4. The method as claimed in claim 3 , wherein the partial trench has a first diameter and the second partial trench has a second diameter, which differs from the first diameter.

5. The method as claimed in claim 4 , wherein the second diameter is less than the first diameter.

6. The method as claimed in claim 1 , wherein the monocrystalline semiconductor layer has a thickness that is less than a depth of the trench etched into the semiconductor substrate.

7. The method as claimed in claim 1 , wherein the semiconductor substrate comprises monocrystalline silicon.

8. The method as claimed in claim 1 , wherein the monocrystalline semiconductor layer comprises monocrystalline silicon.

9. The method as claimed in claim 1 , wherein the trench and the partial trench have a same diameter.

10. The method as claimed in claim 1 , wherein the partial trench has a diameter, which differs from the diameter of the trench.

11. The method as claimed in claim 10 , wherein the diameter of the partial trench is less than the diameter of the trench.

12. The method as claimed in claim 1 , further comprising:

forming a bottom capacitor electrode adjoining the trench wall;

forming a capacitor dielectric adjacent the bottom capacitor electrode; and

forming a top capacitor electrode adjacent the capacitor dielectric, wherein the bottom capacitor electrode, the capacitor dielectric and the top capacitor electrode are each arranged at least partly in the trench.

13. The method as claimed in claim 12 , wherein forming at least one layer on the trench wall comprises said forming a bottom capacitor electrode.

14. The method as claimed in claim 13 , wherein forming at least one layer on the trench wall further comprises providing the capacitor dielectric.

15. The method as claimed in claim 14 , wherein forming at least one layer on the trench wall farther comprises filling the trench with a filling material and covering a surface of the filled trench with the sealing layer.

16. The method as claimed in claim 15 , wherein the filling material is a material suitable for forming a top capacitor electrode.

17. The method as claimed in claim 12 , wherein forming the bottom capacitor electrode, forming the capacitor dielectric and forming the top capacitor electrode are carried out after etching the partial trench in the surface of the epitaxially grown semiconductor layer.

18. The method as claimed in claim 1 , wherein forming at least one layer on the trench wall comprises providing a sacrificial layer.

19. The method as claimed in claim 18 , wherein the sacrificial layer is doped in such a way that it is suitable for effecting a doping of adjoining semiconductor material in a downstream thermal treatment step.

20. The method as claimed in claim 19 , further comprising effecting the doping of the adjoining semiconductor material.

21. The method as claimed in claim 18 , wherein the sacrificial layer comprises silicon dioxide.

22. A method for fabricating an integrated circuit comprising a trench capacitor, the method comprising:

etching a trench into a surface of a semiconductor substrate, wherein a trench wall is exposed;

forming at least one layer on the trench wall, wherein a topmost layer is a sealing layer made of a sealing material;

performing a selective epitaxy method in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate;

etching a partial trench in a surface of the epitaxially grown semiconductor layer, wherein at least part of the sealing layer is uncovered;

removing the uncovered part of the sealing layer;

forming a bottom capacitor electrode in the semiconductor substrate and the epitaxially grown semiconductor layer;

forming a capacitor dielectric adjacent the bottom capacitor electrode; and

forming a top capacitor electrode adjacent the capacitor dielectric, wherein the capacitor dielectric and the top capacitor electrode are arranged at least partly in the trench and the partial trench.

23. The method as claimed in claim 22 , wherein the selective epitaxy method is performed in such a way that the sealing layer is overgrown.

24. The method as claimed in claim 22 , wherein the trench has a depth and a smallest diameter and the ratio of the depth to the smallest diameter is greater than 70.

25. The method as claimed in claim 4 , wherein the first diameter is less than the diameter of the trench.

26. The method as claimed in claim 1 , wherein the selective epitaxy method is performed such that a surface of the trench that is covered by the sealing material is overgrown.

27. The method as claimed in claim 1 , wherein

the unfilled stack trench has a depth and a smallest diameter, wherein the ratio of the depth to the smallest diameter is greater than 70.

28. The method as claimed in claim 27 , wherein the ratio of the depth to the smallest diameter is greater than 80.

29. The method as claimed in claim 28 , wherein the ratio of depth to smallest diameter is greater than or equal to 85.

30. The method of claim 22 , further comprising forming a selection transistor with a first source/drain electrode, a second source/drain electrode, a conductive channel and a gate electrode, the top capacitor electrode being electrically conductively connected to the first source/drain electrode of the selection transistor.