MTJ stack with crystallization inhibiting layer

1. A method of manufacturing a magnetic stack of a resistive memory device over a workpiece, the method comprising:

depositing a first magnetic material layer over the workpiece;

depositing a tunnel insulator over the first magnetic material layer;

depositing a second magnetic material layer over the tunnel insulator; and

depositing a crystallization inhibiting layer over the second magnetic material layer,

wherein the crystallization inhibiting layer comprises a material selected from the group consisting of: 1) materials of the form MSiN, wherein M is a metal; 2) TaCo; 3) TiPN 2 ; 4) W 85 Si 15 ; 5) IrTa; and 6) TaRu.

2. The method according to claim 1 , wherein the crystallization inhibiting layer comprises a material of the form MSiN, where M comprises Ta, Ti, Mo, or W.

3. The method according to claim 1 , wherein depositing the crystallization inhibiting layer comprises depositing a material that crystallizes at a temperature of about 400 to 450 degrees C. or greater.

4. The method according to claim 1 , wherein the crystallization inhibiting layer crystallizes at a first temperature, wherein the second magnetic material layer crystallizes at a second temperature, wherein the first temperature is higher than the second temperature.

5. The method according to claim 1 , wherein depositing the crystallization inhibiting layer comprises depositing an amorphous material.

6. The method according to claim 1 , wherein depositing the crystallization inhibiting layer comprises depositing a material having a thickness of about 200 Angstroms or less.

7. The method according to claim 1 , further comprising disposing a cap layer over the crystallization inhibiting layer.

8. The method according to claim 7 , wherein disposing the cap layer comprises disposing Ta, TaN, Ti, TiN, or combinations thereof.

9. The method according to claim 1 , further comprising:

depositing a pinning layer over the workpiece, before depositing the first magnetic material layer.

10. The method according to claim 9 , wherein depositing the pinning layer comprises depositing a bottom electrode material, and depositing an antiferromagnetic material over the bottom electrode material.

11. The method according to claim 1 , further comprising depositing a top electrode material over the crystallization inhibiting layer.

12. The method according to claim 11 , wherein depositing the top electrode material comprises depositing a conductive hard mask over the crystallization inhibiting layer, further comprising using the conductive hard mask as a mask to pattern the crystallization inhibiting layer and at least the second magnetic material layer.

13. The method according to claim 1 , wherein depositing the first magnetic material layer or depositing the second magnetic material layer comprise forming a first magnetic layer, forming a non-magnetic spacer layer over the first magnetic layer, and forming a second magnetic layer over the non-magnetic spacer layer.

14. The method according to claim 1 , further comprising patterning the magnetic stack to form at least one resistive memory element.

15. The method according to claim 14 , wherein patterning the magnetic stack comprises forming a plurality of magnetic random access memory (MRAM) cells, wherein the MRAM cells comprise a FET MRAM array or a crosspoint MRAM array.

16. A magnetic stack of a resistive memory device, comprising:

a first magnetic material layer;

a tunnel insulator disposed over the first magnetic material layer;

a second magnetic material layer disposed over the tunnel insulator; and

a crystallization inhibiting layer disposed over the second magnetic material layer,

wherein the crystallization inhibiting layer comprises a material selected from the group consisting of: 1) materials of the form MSiN, wherein M is a metal; 2) TaCo; 3) TiPN 2 ; 4) W 85 Si 15 ; 5) IrTa; and 6) TaRu.

17. The magnetic stack according to claim 16 , wherein the crystallization inhibiting layer comprises a material of the form MSiN, where M comprises Ta, Ti, Mo, or W.

18. The magnetic stack according to claim 16 , wherein the crystallization inhibiting layer comprises a material that crystallizes at a temperature of about 400 to 450 degrees C. or greater.

19. The method according to claim 16 , wherein the crystallization inhibiting layer crystallizes at a first temperature, wherein the second magnetic material layer crystallizes at a second temperature, wherein the first temperature is higher than the second temperature.

20. The magnetic stack according to claim 16 , wherein the crystallization inhibiting layer comprises an amorphous material.

21. The magnetic stack according to claim 16 , wherein the crystallization inhibiting layer comprises a material having a thickness of about 200 Angstroms or less.

22. The magnetic stack according to claim 16 , further comprising a cap layer disposed over the crystallization inhibiting layer.

23. The magnetic stack according to claim 22 , wherein the cap layer comprises Ta, TaN, Ti, TiN, or combinations thereof.

24. The magnetic stack according to claim 16 , further comprising a pinning layer disposed beneath the first magnetic material layer.

25. The magnetic stack according to claim 24 , wherein the pinning layer comprises a bottom electrode material, and an antiferromagnetic material disposed over the bottom electrode material.

26. The magnetic stack according to claim 16 , further comprising a top electrode material disposed over the crystallization inhibiting layer.

27. The magnetic stack according to claim 16 , wherein the first magnetic material layer or the second magnetic material layer comprise a first magnetic layer, a non-magnetic spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the non-magnetic spacer layer.

28. A resistive memory element formed from the magnetic stack of claim 16 .

29. An array of resistive memory elements formed from the magnetic stack of claim 16 .

30. The array according to claim 29 , wherein the array of resistive memory elements comprises a plurality of magnetic random access memory (MRAM) cells, wherein the plurality of MRAM cells comprise a FET MRAM array or a crosspoint MRAM array.