IP Library Granted Patent US 7,316,951
Granted Patent B2
US 7,316,951 · App. 11/191,461 · Granted Jan 8, 2008

Fabrication method for a trench capacitor having an insulation collar

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Quick Facts
Patent No.
US 7,316,951
App. No.
11/191,461
Granted
Jan 8, 2008
Kind
B2
Abstract

The present invention provides a fabrication method for a trench capacitor having an insulation collar ( 10 ) in a silicon substrate ( 1 ), having the steps of: providing a trench ( 5 ) in the silicon substrate ( 1 ); providing the insulation collar ( 10 ) in the upper trench region as far as the top side of the silicon substrate ( 1 ); depositing a layer ( 12 ) made of a metal oxide in the trench ( 5 ); carrying out a thermal treatment for selectively reducing the layer ( 12 ), a region of the layer ( 12 ) that lies below the insulation collar ( 10 ) above the silicon substrate ( 1 ) being reduced and being converted into a first capacitor electrode layer ( 15 ) made of a corresponding metal silicide, and a region of the layer ( 12 ) that lies above the insulation collar ( 10 ) not being reduced; selectively removing the non-reduced region of the layer ( 12 ) that lies above the insulation collar ( 10 ); providing a capacitor dielectric layer ( 18 ) in the trench ( 5 ) above the first capacitor electrode layer ( 15 ); and providing a second capacitor electrode layer ( 20 ) in the trench ( 5 ) above the capacitor dielectric layer ( 18 ).

Claims (15)

1. Fabrication method for a trench capacitor having an insulation collar in a silicon substrate, having the steps of:

(a) providing a trench in the silicon substrate;

(b) providing the insulation collar in the upper trench region as far as the top side of the silicon substrate;

(c) depositing a layer made of a metal oxide in the trench, said layer comprising a rare earth oxide;

(d) carrying out a thermal treatment for selectively reducing the layer, a region of the layer that lies below the insulation collar above the silicon substrate being reduced and being converted into a first capacitor electrode layer made of a corresponding metal silicide, and a region of the layer that lies above the insulation collar not being reduced;

(e) removing selectively the non-reduced region of the layer that lies above the insulation collar;

(f) providing a capacitor dielectric layer in the trench above the first capacitor electrode layer; and

(g) providing a second capacitor electrode layer in the trench above the capacitor dielectric layer.

2. Method according to claim 1 , wherein the capacitor dielectric layer comprises Al 2 O 3 .

3. Method according to claim 1 , wherein the capacitor dielectric layer comprises a rare earth oxide, HfO 2 , or a mixture of said oxides with Al 2 O 3 .

4. Method according to claim 1 , wherein the second capacitor electrode layer comprises Si or TiN.

5. Method according to claim 1 , wherein the thermal treatment takes place in the temperature range from 400 to 1100° C. under a hydrogen atmosphere.

6. Method according to claim 1 , wherein the layer is deposited by means of the ALD method.

7. Method according to claim 1 , wherein the capacitor dielectric layer is deposited by means of the ALD or CVD method.

8. Method according to claim 1 , wherein the second capacitor electrode layer is deposited by means of the ALD or CVD method.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2005
From: GUTSCHE, MARTIN; SEIDL, HARALD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016815/0074 →