Parallel data path architecture

1. A memory device, comprising:

a memory array comprising a plurality of memory cells configured to store data;

a plurality of data pads configured to supply as an output of the memory device data retrieved from the memory array in a read operation;

a plurality of parallel read data paths each coupled between the memory array and the data pads, the parallel read data paths including: a plurality of synchronous data paths operable in different modes of operation and an asynchronous data path; and

a mode selector configured to select one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

2. The memory device of claim 1 , wherein the memory device is a pseudo-SRAM.

3. The memory device of claim 1 , wherein the plurality of synchronous data paths includes a first synchronous data path operable over a first range of clock frequencies and a second synchronous data path operable over a second range of clock frequencies that is higher than the first range of clock frequencies.

4. The memory device of claim 1 , wherein the plurality of synchronous data paths includes a first synchronous data path operable in a latched mode, and a second synchronous data path operable in a first-in-first-out (FIFO) mode.

5. The memory device of claim 1 , wherein the mode selector selects the asynchronous data path in response to the absence of an external clock signal.

6. The memory device of claim 1 , wherein the plurality of synchronous data paths includes first and second synchronous data paths, and wherein, in the presence of an external clock signal, the mode selector selects the first synchronous data path in response to a column access strobe (CAS) latency command having a first value, and selects the second synchronous data path in response to the CAS latency command having a second value.

7. A memory device, comprising:

a memory array comprising a plurality of memory cells configured to store data;

a plurality of data pads configured to supply as an output of the memory device data retrieved from the memory array in a read operation;

a plurality of parallel read data paths each coupled between the memory array and the data pads, the parallel read data paths including: an asynchronous data path, a first synchronous data path operable in a latched mode over a first range of clock frequencies, and a second synchronous data path operable in a first-in-first-out (FIFO) mode over a second range of clock frequencies that is higher than the first range of clock frequencies; and

a mode selector configured to select one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

8. The memory device of claim 7 , wherein the memory device is a pseudo-SRAM.

9. The memory device of claim 7 , wherein the mode selector selects the asynchronous data path in response to the absence of an external clock signal.

10. The memory device of claim 7 , wherein, in the presence of an external clock signal, the mode selector selects the first synchronous data path in response to a column access strobe (CAS) latency command having a first value and selects the second synchronous data path in response to the CAS latency command having a second value.

11. A memory device, comprising:

a memory array comprising a plurality of memory cells configured to store data;

a plurality of data pads configured to supply as an output of the memory device data retrieved from the memory array in a read operation;

a plurality of parallel read data paths each coupled between the memory array and the data pads, the parallel read data paths including an asynchronous data path and a plurality of synchronous data paths; and

a mode selector configured to select one of the parallel read data paths to supply data retrieved from the memory array to the data pads, wherein the mode selector selects the asynchronous data path in response to the absence of an external clock signal, and, in the presence of an external clock signal, selects one of the synchronous data paths as a function of a value of a column access strobe (CAS) latency command.

12. The memory device of claim 11 , wherein the memory device is a pseudo-SRAM.

13. The memory device of claim 11 , wherein the plurality of synchronous data paths includes a first synchronous data path that operates in a latched mode and a second synchronous data path that operates in a first-in-first-out (FIFO) mode.

14. A pseudo static random access memory (pseudo-SRAM), comprising:

a memory array comprising a plurality of memory cells configured to store data;

a plurality of data pads configured to supply as an output of the memory device data retrieved from the memory array in a read operation;

a plurality of parallel read data paths each coupled between the memory array and the data pads, the parallel read data paths including: an asynchronous data path, a first synchronous data path operable in a latched mode over a first range of clock frequencies, and a second synchronous data path operable in a first-in-first-out (FIFO) mode over a second range of clock frequencies that is higher than the first range of clock frequencies; and

a mode selector configured to select one of the parallel read data paths to supply data retrieved from the memory array to the data pads, wherein the mode selector selects the asynchronous data path in response to the absence of an external clock signal, and, in the presence of an external clock signal, selects one of the first and second synchronous data paths as a function of a value of a column access strobe (CAS) latency command.

15. A memory device, comprising:

means for storing data;

output means for supplying as an output of the memory device data retrieved from the means for storing data;

a plurality of parallel read data paths each coupled between the means for storing data and the output means, the parallel read data paths including: a plurality of synchronous data paths operable in different modes of operation and an asynchronous data path; and

means for selecting one of the parallel read data paths to supply data retrieved from the means for storing data to the output means.

16. The memory device of claim 15 , wherein the memory device is a pseudo-SRAM.

17. The memory device of claim 15 , wherein the plurality of synchronous data paths includes a first synchronous data path operable over a first range of clock frequencies and a second synchronous data path operable over a second range of clock frequencies that is higher than the first range of clock frequencies.

18. The memory device of claim 15 , wherein the plurality of synchronous data paths includes a first synchronous data path operable in a latched mode, and a second synchronous data path operable in a first-in-first-out (FIFO) mode.

19. The memory device of claim 15 , wherein the means for selecting selects the asynchronous data path in response to the absence of an external clock signal.

20. The memory device of claim 15 , wherein the plurality of synchronous data paths includes first and second synchronous data paths, and wherein, in the presence of an external clock signal, the means for selecting selects the first synchronous data path in response to a column access strobe (CAS) latency command having a first value, and selects the second synchronous data path in response to the CAS latency command having a second value.

21. A method of performing a read operation in a memory device, comprising:

(a) retrieving data from a memory array in response to receipt of a read command;

(b) selecting an asynchronous data path to supply the retrieved data to pads of the memory device in response to the absence of an external clock signal; and

(c) selecting one of a plurality of synchronous data paths to supply the retrieved data to the pads of the memory device in response to detection of an external clock signal, wherein said one of the plurality of synchronous data paths is selected as a function of an external signal received by the memory device.

22. The method of claim 21 , wherein the external signal is a column access strobe (CAS) latency signal.

23. The method of claim 22 , wherein the plurality of synchronous data paths includes first synchronous data path operable in a latched mode and a second synchronous data path operable in a first-in-first-out (FIFO) mode, and wherein (c) includes selecting the first synchronous data path in response to the CAS latency signal having a first value, and selecting the second synchronous data path in response to the CAS latency signal having a second value.

24. The method of claim 23 , wherein the first synchronous data path is operable over a first range of clock frequencies and the second synchronous data path is operable over a second range of clock frequencies that is higher than the first range of clock frequencies.

25. A method of manufacturing a memory device, comprising:

(a) providing a plurality of parallel read data paths each coupled between a memory array and a plurality of data pads of the memory device, the parallel read data paths including a plurality of synchronous data path operable in different modes of operation and an asynchronous data path; and

(b) providing a mode selector for selecting one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

26. The method of claim 25 , wherein (a) includes providing a first synchronous data path operable in a latched mode and a second synchronous data path operable in a first-in-first-out (FIFO) mode.

27. The method of claim 25 , wherein the mode selector selects the asynchronous data path in response to the absence of an external clock signal.

28. The method of claim 25 , wherein (a) includes providing first and second synchronous data paths, and wherein, in the presence of an external clock signal, the mode selector selects the first synchronous data path in response to a column access strobe (CAS) latency signal having a first value, and selects the second synchronous data path in response to the CAS latency signal having a second value.