IP Library Granted Patent US 7,457,589
Granted Patent B2
US 7,457,589 · App. 11/000,323 · Granted Nov 25, 2008

Circuit and method for transmitting a signal

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Quick Facts
Patent No.
US 7,457,589
App. No.
11/000,323
Granted
Nov 25, 2008
Kind
B2
Abstract

A circuit for transmitting a signal has a first signal line and a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place. The circuit further comprises a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay. A second driver is configured for driving a second signal on the second signal line depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal. A method and computer program are also disclosed.

Claims (53)

1. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay;

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal; and

a memory unit for storing a delay information about the delay of the first signal, wherein the memory unit is configured to provide the delay information to the second driver.

2. The circuit according to claim 1 , wherein the second driver is configured to drive the second signal in phase with the first signal, such that the delay of the first signal is reduced.

3. The circuit according to claim 1 , wherein the second driver is configured to drive the second signal in counter phase with the first signal, such that the delay of the first signal is increased.

4. The circuit according to claim 1 , wherein the second driver is configured to drive the second signal at a static level, such that the delay of the first signal is unchanged.

5. The circuit according to claim 1 , wherein the second signal line is arranged physically adjacent to the first signal line such that cross-talk between signals being transmitted on the signal lines takes place.

6. The circuit according to claim 1 , wherein only a portion of the first signal line is physically adjacent the second signal line, the portion comprising less than all of the first signal line.

7. The circuit according to claim 1 , further comprising a third signal line, wherein the third signal line is arranged adjacent to the first signal line such that an interaction between signals being transmitted on the first and third signal lines takes place; and

a third driver driving a third signal on the third line, wherein the third driver is configured to drive the third signal depending on the delay of the first signal, such that the delay of the first signal is further adjusted due to the interaction of the third signal on the first signal.

8. The circuit according to claim 7 , wherein the third driver is configured to drive the third signal in phase or in counter phase to the second signal, such that the delay of the first signal is further increased or decreased, or is configured to drive the third signal on a static level, such that the delay of the first signal is not further changed.

9. The circuit according to claim 1 , further comprising a coupling element for increasing the interaction between the first and second signal lines, wherein the coupling element is connected to the first signal line and to the second signal line.

10. The circuit according to claim 9 , wherein the coupling element comprises a capacitor.

11. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay; and

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal, wherein the second driver comprises a driver resistance and is configured to change the driver resistance depending on the delay of the first signal in order to fine adjust the interaction of the second signal onto the first signal.

12. The circuit according to claim 11 , further comprising a capacitor connected to the first signal line and to the second signal line.

13. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay;

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal; and

a receiver for receiving the first signal, wherein the receiver is configured to determine the delay of the first signal and to provide a delay information to the second driver.

14. The circuit according to claim 13 , wherein the circuit comprises a delay locked loop for adjusting the first signal to a strobe signal, and wherein the delay information is a delay difference between the first signal and the strobe signal.

15. The circuit according to claim 13 , further comprising a memory unit for storing a delay information about the delay of the first signal, wherein the memory unit is configured to provide the delay information to the second driver.

16. The circuit according to claim 13 , further comprising a coupling element for increasing the interaction between the first and second signal lines, wherein the coupling element is connected to the first signal line and to the second signal line.

17. The circuit according to claim 16 , wherein the coupling element comprises a capacitor.

18. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a third signal line, wherein the third signal line is arranged adjacent to the first signal line such that an interaction between signals being transmitted on the first and third signal lines takes place, wherein the first line is arranged between the second and third lines and wherein the lines are arranged on a common plane;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay;

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal; and

a third driver driving a third signal on the third line, wherein the third driver is configured to drive the third signal depending on the delay of the first signal, such that the delay of the first signal is further adjusted due to the interaction of the third signal on the first signal.

19. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay;

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal;

a first receiver coupled to the first signal line such that the first driver drives the first signal to the first receiver; and

a second receiver coupled to the second signal line such that the second driver drives the second signal to the second receiver, wherein the second receiver is a replica of the first receiver.

20. A circuit for transmitting a signal, comprising:

a first signal line;

a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place;

a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay; and

a second driver for driving a second signal on the second line, wherein the second driver is configured to drive the second signal depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal;

a first receiver coupled to the first signal line such that the first driver drives the first signal to the first receiver; and

a second receiver coupled to the second signal line such that the second driver drives the second signal to the second receiver, wherein the second receiver is physically adjacent the first receiver.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036908/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2005
From: KUZMENKA, MAKSIM
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015865/0140 →