Method of treating a structured surface
View Patent ↗The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height. Afterwards the plurality of layers is chemically mechanically polished such that the lower layer is at least partly removed in the first region. By this method achieves a better planarization. Additionally, smaller top contact openings after a wet clean step are achievable and a deformation of contact openings due to annealing steps is reduced.
1. A method of treating a structured surface comprising following steps:
providing a substrate with a structured surface comprising a first region and a second region, wherein an average level of height of the surface in the first region is higher than the second region by a step height;
depositing a plurality of layers on said surface wherein a lower layer exhibits a higher polishing rate than an upper layer and wherein the thickness of the plurality of layers exceeds the step height; and
chemical mechanical polishing of the plurality of layers such that the upper is completely and the lower layer is at least partly removed in the first region.
2. The method according to claim 1 , wherein the plurality of layers is completely removed in the first region by the chemical mechanical polishing.
3. The method according to claim 1 , wherein the upper layer is partly removed in the second region by the chemical mechanical polishing.
4. The method according to claim 1 , wherein layers comprise a silicon oxide glass, wherein a boron concentration in the lower layer is higher than in the upper layer.
5. The method according to claim 1 , wherein an upper layer comprises a nitride and a lower layer comprises silicon oxide.
6. The method according to claim 1 , wherein an upper layer comprises a silicon oxide and a lower layer a low-k dielectric.
7. The method according to claim 1 , wherein contact openings are formed into the plurality of layers such that contact pads on the substrate become exposed.
8. The method according to claim 1 , wherein an annealing step is processed after the deposition of the layers.
9. The method according to claim 1 , wherein an arrangement of semiconductor structures with a high density is arranged in the first region defining the average level of the height of the surface in the first region.
10. The method according to claim 1 , wherein a density of semiconductor structures in the second region is lower than in the first region.
11. The method according to claim 1 , wherein a cell structure of a memory device is arranged in the first region and a logic structure is arranged in the second region.
12. The method according to claim 1 , wherein the plurality of layers is made of two or more separate layers.
13. The method according to claim 1 , wherein the plurality of layers is made of one layer with a continuously increasing polishing rate.
14. The method according to claim 1 , wherein the upper layer comprises a material with a higher glass transition temperature than a lower layer.
15. The method according to claim 1 , wherein a material for an upper layer is chosen such that an etching rate of an etching agent is lower for the upper layer compared to the lower layer.