Ferroelectric memory arrangement

1. A ferroelectric memory arrangement comprising:

a memory cell comprising:

a select transistor; and

a ferroelectric storage capacitor coupled to the select transistor, the ferroelectric storage capacitor including vertical electrodes, and a ferroelectric dielectric between the vertical electrodes, configured wherein a dimension of the ferroelectric dielectric in a lateral direction is approximately equal to a crystallite size of the ferroelectric dielectric material, and wherein the ferroelectric dielectric comprises a plurality of ferroelectric layers having an insulating separating layer between each adjacent ferroelectric layer.

2. The arrangement of claim 1 , comprising wherein a lateral dimension of the plurality of ferroelectric layers is approximately equal to the crystallite size of the plurality of ferroelectric layers.

3. A ferroelectric memory arrangement comprising:

a plurality of memory cells, each memory cell comprising:

a vertical ferroelectric storage capacitor that includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, connected to a select transistor, the ferroelectric dielectric comprising a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer, wherein a lateral dimension of the ferroelectric dielectric layers of each ferroelectric storage capacitor is of the order of magnitude of their crystallite size.

4. The memory arrangement of claim 3 , wherein the ferroelectric dielectric layers are made of Pb(Zr, Ti)O 3 (PZT).

5. The ferroelectric memory arrangement of claim 3 , wherein the ferroelectric dielectric layers are made of (Bi, La) 4 Ti 3 O 12 .

6. The ferroelectric memory arrangement of claim 3 , wherein the ferroelectric dielectric layers are made of (Sr, Bi) 2 Ta 2 O 9 .

7. The ferroelectric memory arrangement of claim 3 , wherein the material of the insulating separating layers are an oxidic material.

8. The ferroelectric memory arrangement of claim 7 , wherein the material of the separating layers consists of Al 2 O 3 .

9. The ferroelectric memory arrangement claim 7 , wherein the material of the separating layers consists of TiO 2 .

10. The ferroelectric memory arrangement of claim 7 , wherein the material of the separating layers consists of Ta 2 O 5 .

11. The ferroelectric memory arrangement of claim 7 , wherein the material of the separating layers consists of CeO 2 .

12. The ferroelectric memory arrangement of claim 7 , wherein the material of the separating layers consists of Y 2 O 3 .

13. The ferroelectric memory arrangement of claim 3 , wherein the layer thickness of the ferroelectric dielectric layers is greater than the layer thickness of the insulating separating layers.

14. The ferroelectric memory arrangement of claim 3 , wherein the alternating layers of the ferroelectric dielectric and the separating layers are located horizontally between the vertical electrodes.

15. A ferroelectric memory arrangement comprising:

a plurality of memory cells, each memory cell comprising:

a vertical ferroelectric storage capacitor that includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, connected to a select transistor, the ferroelectric dielectric comprising a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer, wherein a lateral dimension of the ferroelectric dielectric layers of each ferroelectric storage capacitor is of the order of magnitude of their crystallite size, wherein the number of ferroelectric dielectric layers is selected as a function of a thickness of the ferroelectric dielectric layer and crystallite size.