Charge-trapping semiconductor memory device
View Patent ↗Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.
1. A charge-trapping semiconductor memory cell, comprising:
a semiconductor region having a main surface;
a recess dedicated to a single memory cell in the semiconductor region, the recess extending perpendicularly to said main surface into the semiconductor region and having a sidewall and a bottom area that is at a selected distance from said main surface;
a memory layer sequence arranged at least in an area of said sidewall of said recess;
a gate electrode arranged within said recess;
an upper source/drain region located at an upper part of said sidewall adjacent to said main surface; and
a lower source/drain region located at a lower part of said sidewall adjacent to said bottom area.
2. The charge-trapping semiconductor memory cell according to claim 1 , further comprising means provided for the application of voltages to said gate electrode, said upper source/drain region and said lower source/drain region.
3. The charge-trapping semiconductor memory cell according to claim 1 , wherein said recess has a cylindrical shape.
4. The charge-trapping semiconductor memory cell according to claim 3 wherein the bottom area of the recess is rounded.
5. The charge-trapping semiconductor memory cell according to claim 1 , further comprising a contact plug arranged within the semiconductor region and contacting said lower source/drain region.
6. The charge-trapping semiconductor memory cell according to claim 5 , further comprising a conductive line extending above the main surface, the conductive line coupled to the contact plug.
7. The charge-trapping semiconductor memory cell according to claim 1 , wherein said upper source/drain region has an upper boundary surface that is located within said main surface.
8. The charge-trapping semiconductor memory cell according to claim 1 , wherein the semiconductor region comprises a semiconductor substrate.
9. The charge-tapping semiconductor memory cell according to claim 1 , wherein the semiconductor region comprises a semiconductor layer.
10. The charge-trapping semiconductor memory cell according to claim 1 , wherein the memory layer sequence comprises a dielectric sequence including a first oxide layer, a nitride layer and a second oxide layer.
11. A charge-trapping semiconductor memory device comprising:
a semiconductor region including an array of memory cells arranged rows and columns being formed therein, said array of memory or cells being further grouped in selected pairs of adjacent or neighboring columns, and each memory cell of each pair including a dedicated recess that is provided with a memory layer sequence disposed within at least an area of a sidewall of the recess, a gate electrode within the recess, an upper source/drain region in the semiconductor region adjacent an upper portion of the recess, and a lower source/drain region in the semiconductor region adjacent a lower portion of the recess, said lower source/drain regions of each of said selected pairs formed by a continuous doped region within said semiconductor region;
an array of first bit lines arranged parallel to one another, each first bit line being provided with a plurality of electric connections to a plurality of said upper source/drain regions that are arranged along one of said columns;
an array of second bit lines arranged parallel to said first bit lines, each second bit line being provided with a plurality of electric connections to a plurality of said lower source/drain regions that are arranged along one of said columns; and
an array of word lines arranged parallel to one another, each word line being provided with a plurality of electric connections to a plurality of said gate electrodes that are arranged along one of said rows.
12. The charge-trapping semiconductor memory device according to claim 11 , wherein:
said second bit lines each being provided for one of said pairs of neighboring columns;
a plurality of contact plugs being provided for each second bit line; and
said contact plugs being arranged so as to contact said continuous doped region of lower source/drain regions in areas located between four adjacent ones of said recesses.
13. The charge-trapping semiconductor memory device according to claim 11 , wherein the array of first bit lines, the array of second bit lines and the array of word lines are arranged in three wiring layers at different levels relative to an upper surface of the semiconductor region.
14. The charge-trapping semiconductor memory device according to claim 11 , wherein the bit lines of the array of second bit lines are elevated above the upper surface of the semiconductor region.
15. The charge-trapping semiconductor memory device according to claim 11 , wherein the bit lines of the array of second bit lines comprise buried bit lines within the semiconductor region, the second bit lines directly connecting ones of the lower source/drain regions.
16. The charge-trapping semiconductor memory device according to claim 11 , wherein the memory layer sequence comprises a dielectric sequence including a first oxide layer, a nitride layer and a second oxide layer.
17. The charge-trapping semiconductor memory device according to claim 11 , wherein the array of memory cells has a bit density of 3F 2 /bit, where F is a minimum feature size.
18. A charge-trapping semiconductor memory device comprising:
a semiconductor region including an array of memory cells formed therein, each memory cell including cylindrically shaped dedicated recess that is provided with a memory layer sequence disposed within at least an area of a sidewall of the recess, a gate electrode within the recess, an upper source/drain region in the semiconductor region adjacent an upper portion of the recess, and a lower source/drain region in the semiconductor region adjacent a lower portion of the recess, the array of recesses being arranged in rows and columns;
an array of first bit lines arranged parallel to one another, each first bit line being provided with a plurality of electric connections to a plurality of said upper source/drain regions that are arranged along one of said columns;
an array of second bit lines arranged parallel to said first bit lines, each second bit line being provided with a plurality of electric connections to a plurality of said lower source/drain regions that are arranged along one of said columns; and
an array of word lines arranged parallel to one another, each word line being provided with a plurality of electric connections to a plurality of said gate electrodes that are arranged along one of said rows.