IP Library Granted Patent US 7,273,805
Granted Patent B2
US 7,273,805 · App. 11/137,783 · Granted Sep 25, 2007

Redistribution layer with microstrips

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Quick Facts
Patent No.
US 7,273,805
App. No.
11/137,783
Granted
Sep 25, 2007
Kind
B2
Abstract

A semiconductor device includes a completed semiconductor chip and a dielectric layer overlying the completed semiconductor chip. A redistribution layer overlies the completed semiconductor chip and is embedded in the dielectric layer. The redistribution layer includes a plurality of microstrip conductors. Each microstrip conductor has a height and a width selected such that the height is at least twice the width. In addition, each microstrip conductor is separated from an adjacent microstrip conductor by a spacing distance that is at least twice the width.

Claims (16)

1. A method of making a semiconductor device, the method comprising:

fabricating a semiconductor integrated circuit that includes an uppermost metallization level;

forming a dielectric layer over the semiconductor integrated circuit and over the uppermost metallization;

forming a plurality of trenches in the dielectric layer, each of the trenches having a width and a depth that is greater than the width, a bottom surface of the trench being electrically isolated from the uppermost metallization; and

filling the trenches with a conductor, the conductor serving as a redistribution layer that reroutes contact areas in the uppermost metallization.

2. The method of claim 1 , wherein filling the trenches comprises:

depositing a seed layer within the trenches; and

electrodepositing the conductor over the seed layer.

3. The method of claim 2 , wherein depositing a seed layer within the trenches further deposits a seed layer over an upper surface of the dielectric layer outside the trenches, the method further comprising forming a masking layer over the upper surface of the dielectric layer to prevent the conductor from being electrodeposited on the upper surface.

4. The method of claim 2 , wherein the conductor comprises copper.

5. The method of claim 1 , wherein forming a plurality of trenches comprises forming substantially rectangular shaped trenches, wherein the ratio of the depth to the width of each trench is at least 4:1.

6. The method of claim 1 , wherein forming a plurality of trenches comprises forming trenches that have sloping sidewalls.

7. The method of claim 6 , wherein forming a plurality of trenches comprises forming a plurality of v-shaped trenches.

8. The method of claim 1 , wherein forming a dielectric layer comprises forming a polymer layer.

9. The method of claim 8 , wherein forming a dielectric layer comprises forming a photoresist layer.

10. The method of claim 1 , wherein the ratio of the depth of the trench to the width of the trench is between about 2:1 and 10:1 and wherein each trench is separated from a closest adjacent trench by at least a minimum spacing distance, wherein the ratio of the minimum spacing distance to the width of the trench is at least 5:1.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036908/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2005
From: GROSS, HARALD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016638/0164 →