Semiconductor memory system with a variable and settable preamble f
View Patent ↗The present invention relates to a method for operating a semiconductor memory apparatus, comprising: transmitting a command instruction, particularly a write instruction and/or a read instruction, to the semiconductor memory apparatus; transmitting a data signal to and/or from the semiconductor memory apparatus; and transmitting a data clock signal is transmitted for the purpose of latching the data signal; wherein the preamble (P), which is the number of clock cycles between the first edge of the data clock signal (WQDS) and the first bit (D 0 ) of the data signal (DQ), can be set. The invention also relates to a semiconductor memory system comprising a semiconductor memory apparatus and a processor unit configured to perform the method.
1. A method for operating a semiconductor memory apparatus, comprising:
transmitting a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
communicating a data signal with the semiconductor memory apparatus;
transmitting a data clock signal to latch the data signal; and
setting a preamble, wherein the preamble is a period of time between a first edge of the data clock signal and a first bit of the data signal, and wherein the data clock signal is present only during a read or write operation initiated by the command instruction and during which data is read or written from or to the semiconductor memory apparatus, wherein setting the preamble comprises setting a number of clock cycles of the data clock signal in the period of time defined by the preamble.
2. The method of claim 1 , wherein the preamble is set utilizing a configuration instruction.
3. The method of claim 2 , wherein the configuration instruction contains at least one bit for setting the preamble.
4. The method of claim 3 , wherein the preamble is set to equal to a latency which represents the number of clock cycles between the command instruction and the first edge of the data signal.
5. The method of claim 3 , wherein the preamble is set to be greater than a latency which represents the number of clock cycles between the command instruction and the first edge of the data signal.
6. A system, comprising:
a semiconductor memory apparatus;
a processor unit which is configured to:
transmit a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
communicate a data signal with the semiconductor memory apparatus;
transmit a data clock signal to latch the data signal; and
set a preamble, wherein the preamble is a period of time between a first edge of the data clock signal and a first bit of the data signal, and wherein the data clock signal is present only during a read or write operation initiated by the command instruction and during which data is read or written from or to the semiconductor memory apparatus, wherein the preamble is set by setting a number of clock cycles of the data clock signal in the period of time defined by the preamble.
7. The system of claim 6 , wherein the preamble is set utilizing a configuration instruction.
8. The system of claim 7 , wherein the configuration instruction contains at least one bit for setting the preamble.
9. The system of claim 8 , wherein the preamble is set to equal to a latency which represents the number of clock cycles between the command instruction and the first edge of the data signal.
10. The system of claim 8 , wherein the preamble is set to be greater than a latency which represents the number of clock cycles between the command instruction and the first edge of the data signal.
11. A method for operating a semiconductor memory apparatus, comprising:
transmitting a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
communicating a data signal with the semiconductor memory apparatus;
transmitting a data clock signal to latch the data signal; and
transmitting a configuration instruction to the semiconductor memory apparatus, wherein the configuration instruction sets a mode register value selected from at least two predefined values; wherein each of the predefined values sets a preamble length, wherein the preamble length is a period of time between a first edge of the data clock signal and a first bit of the data signal, and wherein the data clock signal is present only during a read or write operation initiated by the command instruction and during which data is read or written from or to the semiconductor memory apparatus, wherein each of the predefined values sets the preamble length by setting a number of clock cycles of the data clock signal in the period of time defined by the preamble length.