Memory circuit receivers activated by enable circuit

1. A memory circuit comprising:

an enable circuit configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level; and

a receiver configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal,

wherein the receiver comprises:

a first current source; and

a switch coupled to the first current source, the switch configured to enable the first current source in response to the first logic level of the enable signal and disable the first current source in response to the second logic level of the enable signal.

2. The memory circuit of claim 1 , wherein the receiver further comprises:

a second current source configured to maintain the receiver in a standby mode in response to the second logic level of the enable signal.

3. The memory circuit of claim 2 , wherein the first current source provides a first current and the second current source provides a second current, and wherein the first current is greater than the second current.

4. The memory circuit of claim 1 , further comprising:

a clock receiver configured to receive a differential external clock signal and provide the internal clock signal.

5. The memory circuit of claim 1 , wherein the receiver comprises an address receiver.

6. The memory circuit of claim 1 , wherein the receiver comprises a command receiver.

7. The memory circuit of claim 1 , wherein the receiver comprises a bank select receiver.

8. A memory circuit comprising:

an enable circuit configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level; and

a receiver configured to bc activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal,

wherein the enable circuit comprises:

a first delay configured to delay a rising edge of the internal clock signal to provide a rising edge of the enable signal; and

a second delay configured to delay a falling edge of the internal clock signal to provide a falling edge of the enable signal.

9. A memory circuit comprising:

an address receiver configured to be selectively activated in response to an enable signal;

a command receiver configured to be selectively activated in response to the enable signal;

a bank select receiver configured to be selectively activated in response to the enable signal;

a clock receiver configured to receive a differential external clock signal and provide an internal clock signal;

an enable circuit configured to receive the internal clock signal and provide the enable signal to activate the address receiver, the conimand receiver, and the bank select receiver during a setup and hold time of the address receiver, the command receiver, and the bank select receiver; and

a memory coupled the address receiver, the command receiver, and the bank select receiver.

10. The memory circuit of claim 9 , wherein the memory comprises a dynamic random access memory.

11. The memory circuit of claim 9 , wherein the memory comprises a mobile random access memory.

12. The memory circuit of claim 9 , wherein the memory comprises a pseudo-static random access memory.

13. The memory circuit of claim 12 , wherein the memory comprises a cellular random access memory.

14. A method for receiving a signal in a memory circuit, the method comprising:

receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level; and

activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to the second logic level of the enable signal,

wherein activating the receiver comprises switching on a current source of the receiver in response to the first logic level of the enable signal, and wherein deactivating the receiver comprises switching off the current source in response to the second logic level of the enable signal.

15. A method for receiving a signal in a memory circuit, the method comprising:

receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level;

activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to the second logic level of the enable signal; and

receiving a differential external clock signal and providing the internal clock signal in response to the differential external clock signal.

16. A method for receiving a signal in a memory circuit, the method comprising:

receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level; and

activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to ihe second logic level of the enable signal,

wherein providing the enable signal comprises delaying a rising edge of the internal clock signal by a first delay to provide a rising edge of the enable signal and delaying a falling edge of the internal clock signal by a second delay to provide a falling edge of the enable signal.

17. A method for receiving a signal in a memory circuit, the method comoprising:

receiving an internal clock signal and providing an enable signal having a first logic level and a second logic level; and

activating a receiver in response to the first logic level of the enable signal and deactivating the receiver in response to the second logic level of the enable signal,

wherein providing the enable signal having the first logic level comprises providing the enable signal having the first logic level during a time equal to a setup and hold time of the receiver.

18. A memory circuit for low power applications comprising:

an address receiver configured to be selectively activated to collect and decode address signals and deactivated to conserve power between the address signals in response to an enable signal;

a command receiver configured to be selectively activated to collect and decode command signals and deactivated to conserve power between command signals in response to the enable signal;

a bank select receiver configured to be selectively activated to collect and decode bank select signals and deactivated to conserve power between bank select signals in response to the enable signal;

a clock receiver configured to receive a differential external clock signal and provide an internal clock signal;

an enable circuit configured to receive the internal clock signal and provide the enable signal to activate the address receiver, the command receiver, and the bank select receiver during a setup and hold time of the address receiver, the command receiver, and the bank select receiver; and

a memory coupled the address receiver, the command receiver, and the bank select receiver.