Power saving refresh scheme for DRAMs with segmented word line architecture
View Patent ↗Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently de-activate (pre-charge) a master wordline each time a corresponding wordline segment is refreshed, the master wordline may remain activated while corresponding wordline segments are refreshed.
1. A method for refreshing memory cells accessed via wordline segments driven by master wordlines, comprising:
activating the master wordline in response to a refresh signal, wherein the activated master wordline is selected based on an internally generated refresh address;
prior to de-activating the master wordline, sequentially activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto; and
de-activating the master wordline as a function of one or more bits of the internally generated refresh address.
2. The method of claim 1 , wherein each of the plurality of segment wordlines are activated prior to receiving another refresh signal.
3. The method of claim 1 , wherein the refresh signal is generated in response to an externally received command.
4. A method for refreshing memory cells accessed via wordline segments driven by master wordlines, comprising:
(a) activating a master wordline selected based on an internally generated refresh address;
(b) prior to de-activating the selected master wordline, activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto;
(c) de-activating the master wordline;
(d) adjusting the refresh address; and
(e) repeating steps (a)–(c) to refresh memory cells connected to wordline segments driven by other master wordlines, wherein de-activating the master wordline comprises de-activating the master wordline as a function of one or more bits of the internally generated refresh address.
5. The method of claim 4 , wherein activating a plurality of wordline segments driven by the master wordline comprises sequentially activating each wordline segment driven by the master wordline, wherein the refresh address is adjusted after each wordline segment activation.
6. A memory device, comprising:
a plurality of memory cells connected to wordline segments driven by master wordlines;
refresh circuitry configured to; and
refresh circuitry configured to select a master wordline for activation based on an internally generated refresh address, activate the selected master wordline in response to a refresh signal and, prior to de-activating the master wordline, sequentially activate a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto, wherein the refresh circuitry is further configured to de-activate the master wordline as a function of one or more bits of the internally generated refresh address.
7. The memory device of claim 6 , wherein the refresh circuitry is configured to de-activate the master wordline only after every wordline segment driven by the master wordline has been activated.
8. The memory device of claim 6 , wherein the refresh circuitry is configured to activate each of the plurality of segment wordlines prior to receiving another refresh signal.
9. The memory device of claim 6 , wherein the refresh signal is generated in response to an externally received command.
10. A memory device, comprising:
a plurality of memory cells connected to wordline segments driven by master wordlines;
refresh circuitry configured to:
(a) activate a master wordline selected based on an internally generated refresh address;
(b) prior to de-activating the selected master wordline, activate a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto;
(c) de-activate the master wordline;
(d) adjust the refresh address; and
(e) repeat steps (a)–(c) to refresh memory cells connected to wordline segments driven by other master wordlines, wherein the refresh circuitry is configured to activate a plurality of wordline segments driven by the master wordline by sequentially activating each wordline segment driven by the master wordline and adjust the refresh address after each wordline segment activation and wherein the refresh circuitry is configured to de-activate the master wordline as a function of one or more bits of the internally generated refresh address.
11. A memory device, comprising:
a plurality of memory cells connected to wordline segments driven by master wordlines;
means for internally generating a refresh address; and
means for activating a master wordline in response to a refresh signal and, prior to de-activating the master wordline, sequentially activating a plurality of wordline segments driven by the master wordline to refresh memory cells connected thereto, wherein the means for activating the master wordline is configured to select master wordlines for activation based on the internally generated refresh address.
12. The memory device of claim 11 , wherein the means for activating the master wordline is configured to de-activate the master wordline only after every wordline segment driven by the master wordline has been activated.
13. The memory device of claim 11 , wherein the means for activating the master wordline is configured to activate each of the plurality of wordline segments prior to receiving another refresh signal.