Sense amplifier bitline boost circuit
View Patent ↗A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
1. A current sense amplifier, comprising:
a voltage comparator having a first input, a second input, and an output;
a first clamping device coupled between the first input of the voltage comparator and a node conducting a first signal, the first clamping device being coupled to a reference voltage;
a second clamping device coupled between the second input of the voltage comparator and a node conducting a second signal, the second clamping device being coupled to the reference voltage;
a current mirror coupled between the first and second input of the voltage comparator; and
a bitline boost circuit, including a source follower and a switch, coupled between the reference voltage and the node conducting the first signal.
2. The current sense amplifier according to claim 1 , wherein the bitline boost circuit is configured to clamp the voltage of the first signal at substantially the same level as the first clamping device.
3. The current sense amplifier according to claim 1 , wherein the source follower includes a source, a gate, and a drain, the gate being coupled to the reference voltage and the source being coupled to the node conducting the first signal.
4. The current sense amplifier according to claim 3 , wherein the drain of the source follower is coupled to the switch, and wherein the switch is coupled to a voltage source.
5. The current sense amplifier according to claim 4 , wherein the switch is controlled to conduct during an initial period of sensing the resistance of a memory cell.
6. The current sense amplifier according to claim 1 , wherein the source follower is configured with an n-type MOSFET and the switch is configured with a p-type MOSFET.
7. The current sense amplifier according to claim 1 , wherein the node conducting the second signal is coupled to at least two reference cells.
8. A memory device comprising the current sense amplifier of claim 1 , the current sense amplifier configured to sense the resistance of a memory cell.
9. The current sense amplifier according to claim 8 , wherein the bitline boost circuit is configured to provide a current to the node conducting the first signal during an initial period of sensing the resistance of the memory cell.
10. The current sense amplifier according to claim 8 , wherein the voltage comparator output indicates the logic state of the memory cell.
11. A method of configuring a current sense amplifier to sense the resistance of a memory cell, comprising:
providing a voltage comparator having a first input, a second input, and an output;
coupling a first clamping device between the first input of the voltage comparator and a node conducting a first signal, coupling the first clamping device to a reference voltage;
coupling a second clamping device between the second input of the voltage comparator and a node conducting a second signal, coupling the second clamping device to a reference voltage;
coupling a current mirror between the first and second input of the voltage comparator; and
coupling a bitline boost circuit, including a source follower and a switch, between the reference voltage and the node conducting the first signal.
12. A method of sensing the resistance of a memory cell configured with at least two logic states, the method, comprising:
receiving a first current signal at a first node;
clamping a voltage of the first node to a voltage related to a reference voltage;
receiving a second current signal at a second node;
clamping a voltage of the second node to the voltage related to the reference voltage;
mirroring the first current signal to a third node that has a high impedance;
combining the mirrored signal at the third node with a signal representing the second current;
determining the logic state of the memory cell from the voltage of the third node; and
boosting the current flowing into the second node by supplying additional current to the second node while maintaining the clamping voltage of the second node to the voltage related to the reference voltage.
13. The method according to claim 12 , wherein the first current signal is proportionately mirrored to the third node.
14. The method according to claim 12 , including boosting the current flowing into the second node during an initial period of sensing the resistance of the memory cell.
15. The method according to claim 12 , wherein the boosted current flowing into the second node is controlled by a switch coupled to a voltage source.
16. The method according to claim 12 , wherein the switch is enabled to conduct during an initial period of sensing the resistance of the memory cell.