Method for producing a semiconductor structure
View Patent ↗In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.
1. A method for producing a semiconductor structure, comprising the steps of:
providing a semiconductor substrate with a top surface on which a gate dielectric layer is provided; on said gate dielectric layer being provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks;
providing a dielectric layer over said memory cell array region and said peripheral element region;
carrying out a first source/drain implantation over said memory cell array region and said peripheral element region;
forming a blocking mask over the memory cell array region;
removing said dielectric layer over said peripheral element region using said blocking mask; and
carrying out a second source/drain implantation over said memory cell array region and said peripheral element region; said memory cell array region being protected by a mask.
2. The method of claim 1 , wherein said mask is a photoresist mask.
3. The method of claim 1 , wherein said mask is said blocking mask.
4. The method of claim 1 , wherein said semiconductor substrate is a silicon substrate and said gate dielectric layer comprises silicon oxide.
5. The method of claim 1 , wherein said dielectric layer comprises silicon oxide.
6. The method of claim 1 , comprising providing a polysilicon mask under said blocking mask in said memory cell array region; said polysilicon mask partially masking some of said gate stacks of said first or second pluralities of gate stacks.
7. The method of claim 1 , comprising providing an isolation region between said memory cell array region and said peripheral element region.
8. The method of claim 7 , wherein said isolation region comprises at least one isolation trench.