Semiconductor memory device, system with semiconductor memory device, and method for operating a semiconductor memory device
View Patent ↗The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a device provided on said semiconductor memory device in support of a high speed operation, as a function of the data value (CL) stored.
1. A method for operating a semiconductor memory device, comprising:
reading out a data value defining a latency time and stored in a memory; and
activating a high speed operation support device, provided on the semiconductor memory device, improving the performance of the semiconductor memory device each time that said data value stored in said memory is greater than a predetermined threshold value.
2. The method according to claim 1 , wherein said memory is a latency time register, and said data value stored in the memory is a latency time data value.
3. The method according to claim 2 , wherein said latency time register is a CAS latency time register, and said data value stored in said latency time register is a CAS latency time data value.
4. The method according to claim 1 , wherein said device is activated if said data value, stored in said memory is greater than to a predetermined threshold value.
5. The method according to claim 1 , wherein said device is deactivated if said data value stored in said memory is smaller than to a predetermined threshold value.
6. The method according to claim 1 , wherein said device is activated if said data value stored in said memory is smaller than to a predetermined threshold value.
7. The method according to claim 1 , wherein said device is deactivated if said data value stored in said memory is greater than to a predetermined threshold value.
8. The method according to claim 1 , wherein said device is a duty cycle correction circuit.
9. The method according to claim 1 , wherein said device is a voltage regulation circuit or part of a voltage regulation circuit.
10. The method according to claim 1 , wherein said device is a receiver circuit or part of a receiver circuit.
11. The method according to claim 1 , wherein said device is an output driver circuit or part of an output driver circuit.
12. A semiconductor memory device comprising:
a memory for storing a data value defining a latency time; and
a controller for activating a high speed operation support device, provided on said semiconductor memory device, improving the performance of the semiconductor memory device, each time that said data value stored in said memory is greater than a predetermined threshold value.
13. A system comprising:
a semiconductor memory device;
a memory for storing a data value; and
a controller for activating high speed operation support device provided on said semiconductor memory device improving the performance of the semiconductor memory device, each time that said data value stored in said memory is greater than, or greater than-equal to a predetermined threshold value.