IP Library Granted Patent US 7,459,376
Granted Patent B2
US 7,459,376 · App. 11/051,969 · Granted Dec 2, 2008

Dissociated fabrication of packages and chips of integrated circuits

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Quick Facts
Patent No.
US 7,459,376
App. No.
11/051,969
Granted
Dec 2, 2008
Kind
B2
Abstract

A method of fabricating a semiconductor component includes providing a prefabricated frame that includes metal traces and lead-through contacts. A semiconductor chip is mounted into the prefabricated frame such that the semiconductor chip is embedded within a rim of the prefabricated frame. Contact regions on a surface of the semiconductor chip are electrically connected with the metal traces of the prefabricated frame such that the contact regions are electrically coupled to the lead-through contacts via the metal traces.

Claims (27)

1. A method of fabricating a semiconductor component, the method comprising:

forming a trace attached to a substrate and made solely of conductive metal, said conductive metal trace having a first end and a second end;

providing a frame structure having a rim at least partially defining a first recess for receiving a semiconductor circuit and a bore;

filling the bore with a solder material to form a lead-through contact;

positioning said bore of said frame structure filled with said solder material to contact said first end of said metal trace on the substrate;

reflowing said solder material filling the bore to attach the first end of the metal trace to the frame structure;

detaching the metal trace from the substrate such that the first end of the metal trace is supported by the rim of the frame structure and the reflowed solder material in said lead-through contact so that the second end of the metal trace is cantilevered over said recess;

adhering a semiconductor chip to a dummy substrate;

positioning the semiconductor chip within the first recess of the frame structure such that said semiconductor chip is embedded within said rim of the frame structure;

attaching the semiconductor chip to the rim of the frame structure;

removing the dummy substrate from the semiconductor chip; and

physically connecting a contact region on a surface of the semiconductor chip directly to the cantilevered second end of said metal trace of the frame structure such that the contact region is electrically coupled to the lead-through contact via the metal trace.

2. The method of claim 1 wherein positioning the semiconductor chip within the first recess of the frame structures comprises placing the frame over the semiconductor chip while the semiconductor chip is substantially stationary.

3. The method of claim 1 and further comprising assembling a second semiconductor component that is substantially identical in structure to the semiconductor component, the method further comprising attaching the second semiconductor component to the semiconductor component.

4. The method of claim 3 , wherein attaching the second semiconductor component to the semiconductor component comprises aligning the semiconductor component and the second semiconductor component in a mechanical jig.

5. The method of claim 3 and further comprising forming a molding compound over the semiconductor component and the second semiconductor component.

6. The method of claim 1 , wherein the contact region is electrically connected with the cantilevered second end of the metal trace by heat and ultrasonic energy.

7. The method of claim 1 , wherein the contact region is electrically connected with the cantilevered second end of the metal trace by ultrasonic compression batch bonding.

8. The method of claim 1 wherein forming the trace attached to the substrate comprises:

forming a sacrificial layer over the substrate;

patterning the sacrificial layer;

depositing a seed layer over the patterned sacrificial layer;

forming metal over the seed layer;

planarizing the metal to expose the patterned sacrificial layer; and

removing the patterned sacrificial layer.

9. The method of claim 8 wherein forming the metal over the seed layer comprises electroplating gold.

10. The method of claim 1 wherein filling the bore with the solder material comprises microinjecting solder into the bore.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036908/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2005
From: GROSS, HARALD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 016218/0183 →