Variable delay line using two blender delays

1. A variable delay line comprising:

a first blender delay configured to provide a first signal;

a second blender delay configured to provide a second signal complementary to the first signal; and

a coarse delay configured to delay the first signal if an even number of coarse delay elements are selected and delay the second signal if an odd number of coarse delay elements are selected,

wherein the first blender delay is configured to interpolate between an early signal and a late signal based on a first control signal to provide the first signal.

2. The variable delay line of claim 1 , wherein the first blender delay is configured to provide a maximum delay for the first signal before the coarse delay switches from an even number of coarse delay elements to an adjacent higher odd number of coarse delay elements.

3. The variable delay line of claim 1 , wherein the first blender delay is configured to provide a minimum delay for the first signal before the coarse delay switches from an odd number of coarse delay elements to an adjacent lower even number of coarse delay elements.

4. The variable delay line of claim 1 , wherein the second blender delay is configured to provide a maximum delay for the second signal before the coarse delay switches from an odd number of coarse delay elements to an adjacent higher even number of coarse delay elements.

5. The variable delay line of claim 1 , wherein the second blender delay is configured to provide a minimum delay for the second signal before the coarse delay switches from an even number of coarse delay elements to an adjacent lower odd number of coarse delay elements.

6. The variable delay line of claim 1 , wherein the second blender delay is configured to provide the second signal having a delay equal to a delay of a coarse delay element minus a delay of the first signal.

7. The variable delay line of claim 1 , wherein the second blender delay is configured to interpolate between the early signal and the late signal based on a second control signal to provide the second signal.

8. The variable delay line of claim 7 , wherein the late signal is delayed with respect to the early signal by a delay of a coarse delay element.

9. The variable delay line of claim 7 , wherein the first control signal is a complement of the second control signal.

10. A circuit comprising:

a first blender delay configured to interpolate between an early signal and a late signal to provide a first signal;

a second blender delay configured to interpolate between the early signal and the late signal to provide a second signal complementary to the first signal; and

a coarse delay comprising a chain of even numbered delay units and odd numbered delay units, the even numbered delay units coupled to the first blender delay to receive the first signal and the odd numbered delay units coupled to the second blender delay to receive the second signal.

11. The circuit of claim 10 , wherein the late signal is delayed with respect to the early signal by a delay of one coarse delay unit.

12. The circuit of claim 10 , wherein the even numbered delay units are selected by an even numbered selection signal and the odd numbered delay units are selected by an odd numbered selection signal.

13. A variable delay comprising:

means for receiving a clock signal;

means for delaying the clock signal by a delay of a coarse delay element to provide a late signal;

means for interpolating between the clock signal and the late signal to provide a first signal based on a first control signal;

means for interpolating between the clock signal and the late signal to provide a second signal based on a second control signal, the second control signal a complement of the first control signal;

means for delaying the first signal through an even number of coarse delay elements if an even number of coarse delay elements are selected; and

means for delaying the second signal through an odd number of coarse delay elements if an odd number of coarse delay elements are selected.

14. A memory circuit comprising:

a delay looked loop comprising a variable delay line, the variable delay line comprising:

a first blender delay configured to provide a first delayed signal;

a second blender delay configured to provide a second delayed signal complementary to the first delayed signal; and

a coarse delay configured to delay the first delayed signal if an even number of coarse delay elements are selected and delay the second delayed signal if an odd number of coarse delay elements are selected; and

a memory coupled to the delay looked loop,

wherein the first blender delay is configured to interpolate between an early signal and a late signal based on a first control signal to provide the first signal.

15. The memory circuit of claim 14 , wherein the memory comprises a synchronous dynamic random access memory.

16. The memory circuit of claim 14 , wherein the memory comprises a double data rate synchronous dynamic random aecess memory.

17. A method for delaying a clock signal through a variable delay line, the method comprising:

receiving a clock signal;

delaying the clock signal by a coarse delay element to provide a late signal;

interpolating between the clock signal and the late signal to provide a first signal based on a first control signal;

interpolating between the clock signal and the late signal to provide a second signal based on a second control signal, the second control signal a complement of the first control signal;

delaying the first signal through an even number of coarse delay elements if an even number of coarse delay elements are selected; and delaying the second signal through an odd number of coarse delay elements if an odd number of coarse delay elements are selected.

18. The method of claim 17 , further comprising:

switching from an even number of coarse delay elements to an adjacent higher odd number of coarse delay elements if the first signal is delayed by one coarse delay element.

19. The method of claim 17 , further comprising:

switching from an odd number of coarse delay elements to an adjacent lower even number of coarse delay elements if the first signal is not delayed.

20. The method of claim 17 , further comprising:

switching from an odd number of coarse delay elements to a adjacent higher even number of coarse delay elements if the second signal is delayed by one coarse delay element.

21. The method of claim 17 , further comprising:

switching from an even number of coarse delay elements to an adjacent lower odd number of coarse delay elements if the second signal is not delayed.

22. A variable delay line comprising:

a first blender delay configured to provide a first signal;

a second blender delay configured to provide a second signal;

a coarse delay configured to delay the first signal if an even number of coarse delay elements are selected and delay the second signal if an odd number of coarse delay elements are selected;

wherein the first blender delay is configured to provide a maximum delay for the first signal before the coarse delay switches from an even number of coarse delay elements to an adjacent higher odd number of coarse delay elements;

wherein the first blender delay is configured to provide a minimum delay for the first signal before the coarse delay switches from an odd number of coarse delay elements to an adjacent lower even number of coarse delay elements;

wherein the first blender delay is configured to interpolate between an early signal and a late signal based on a first control signal to provide the first signal;

wherein the second blender delay is configured to provide a maximum delay for the second signal before the coarse delay switches from an odd number of coarse delay elements to an adjacent higher even number of coarse delay elements; and

wherein the second blender delay is configured to provide a minimum delay for the second signal before the coarse delay switches from an even number of coarse delay elements to an adjacent lower odd number of coarse delay elements.