Semi-conductor component, as well as a process for the in-or output of test data
View Patent ↗The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.
1. A process for inputting and/or outputting test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells for storing useful data, and one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, comprising:
applying a control signal to the semi-conductor component for switching over the semi-conductor component from a first to a second operating mode; and
applying an address signal to the semi-conductor component, wherein in the second operating mode one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal, and in the first operating mode one or more of the useful data memory cells.
2. The process according to claim 1 , wherein in the second operating mode an address space of the test data and/or semi-conductor component operating control data register(s) is mapped in an address space of the useful data memory cell(s).
3. The process according to claim 1 , further comprising:
entering or reading test data and/or semi-conductor component operating control data into or from the register(s) addressed by the address signal.
4. The process according to claim 1 , wherein the first operating mode is a normal operating mode, and the second operating mode a test operating mode.
5. The process according to claim 1 , wherein the semi-conductor component comprises a plurality of useful data memory cells arranged in a memory array area.
6. The process according to claim 1 , wherein the semi-conductor component comprises a plurality of test data and/or semi-conductor component operating control data registers arranged in a test block area.
7. The process according to claim 1 , wherein the semiconductor-component is a memory component.
8. The process according to claim 7 , wherein the semi-conductor component is a RAM.
9. The process according to claim 7 , wherein test data generated during the testing of the semi-conductor component and/or used for the testing of the semi-conductor component is stored in the one or more test data and/or semi-conductor component operating control data registers.
10. A semi-conductor component, comprising:
a plurality of useful data memory cells for storage of useful data;
a plurality of test data and/or semi-conductor component operating control data registers for the storage of test data and/or semi-conductor component operating control data;
a device for mapping an address space of the test data and/or semi-conductor component operating control data registers in an address space of the useful data memory cells.