Driver circuit for binary signals
View Patent ↗The invention relates to a driver circuit for binary signals, said circuit having two branch circuits which are connected in parallel with one another between an input node and an output node, the first of which branch circuits contains an output stage which, in response to the first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a first nonreactive resistor, and the second of which branch circuits contains an output stage which, in response to the second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a second nonreactive resistor. According to the invention, the driver circuit contains a duty ratio control device for setting the signal propagation time from the input node to the output stage of one branch circuit relative to the signal propagation time from the input node to the output stage of the other branch circuit.
1. A driver circuit, comprising:
a first branch circuit disposed between an input node and an output node; wherein the first branch circuit includes a first output stage;
a second branch circuit disposed between the input node and the output node and connected in parallel with to the first branch circuit, wherein the second branch circuit contains a second output; and
a duty ratio control device configured to set a signal propagation time of the binary signal from the input node to the first output stage relative to a signal propagation time of the binary signal from the input node to the second output stage, wherein the duty ratio control device comprises:
a first controllable delay device arranged in the first branch circuit; and
a second controllable delay device arranged in the second branch circuit.
2. The driver circuit of claim 1 , wherein the controllable delay devices are individually controllable.
3. The driver circuit of claim 2 , further comprising:
a first preamplifier connected between the input node and the first controllable delay device; and
a second preamplifier connected between the input node and the second controllable delay device.
4. A driver circuit, comprising:
a first branch circuit disposed between an input node and an output node, the first branch circuit comprising:
a first output stage comprising a first plurality of parallel output drivers, each of which, in response to a first binary value of a binary signal that is applied to the input node, connects the output node to a first logic potential via a respective resistor; and
upstream of the first plurality of output drivers, a first controllable time-staggering device for staggering the input signal to the respective output drivers;
a second branch circuit disposed between the input node and the output node and connected in parallel with to the first branch circuit; wherein second branch circuit comprises:
a second output stage comprising a second plurality of parallel output drivers, each of which, in response to a second binary value of the binary signal that is applied to the input node, connects the output node to a second logic potential via a respective resistor; and
upstream of the second plurality of output drivers, a second controllable time-staggering device for staggering the input signal to the respective output drivers; and
a duty ratio control device for setting a signal propagation time of the binary signal from the input node to the first output stage relative to a signal propagation time of the binary signal from the input node to the second output stage, wherein the duty ratio control device comprises
a first controllable delay device arranged in the first branch circuit between the input node and the first controllable time-staggering device; and
a second controllable delay device arranged in the second branch circuit between the input node and the second controllable time-staggering device.
5. The driver circuit of claim 4 , wherein the controllable delay devices are individually controllable.
6. The driver circuit of claim 4 , further comprising:
a first preamplifier connected between the input node and the first controllable delay device; and
a second preamplifier connected between the input node and the second controllable delay device.
7. A method for operating a driver circuit, comprising:
inputting a binary signal at an input node connected to:
(i) a first branch circuit disposed between the input node and an output node; wherein the first branch circuit includes a first output stage;
(ii) a second branch circuit disposed between the input node and the output node and connected in parallel with to the first branch circuit; wherein the second branch circuit contains a second output; and
responsive to a control signal input to a duty ratio control device, adjusting relative signal characteristics between the binary signal at the input node and the binary signal at the output node, wherein the duty ratio control device comprises:
a first controllable delay device arranged in the first branch circuit; and
a second controllable delay device arranged in the second branch circuit; and wherein adjusting the relative signal characteristics comprises adjusting the delay imposed on the input signal by the respective controllable delay devices.
8. The method of claim 7 , wherein the controllable delay devices are individually controllable.
9. The method of claim 7 , further comprising:
amplifying the signal in the first branch circuit with a first preamplifier connected between the input node and the first controllable delay device; and
amplifying the signal in the second branch circuit with a second preamplifier connected between the input node and the second controllable delay device.
10. An integrated circuit comprising a driver circuit, the driver circuit comprising:
a first branch circuit disposed between an input node and an output node;
a second branch circuit disposed between the input node and the output node and connected in parallel to the first branch circuit; and
a duty ratio control device comprising:
a first controllable delay device arranged in the first branch circuit; and
a second controllable delay device arranged in the second branch circuit.
11. The integrated circuit of claim 10 , wherein the controllable delay devices are individually controllable.
12. The integrated circuit of claim 10 , further comprising:
a first preamplifier connected between the input node and the first controllable delay device; and
a second preamplifier connected between the input node and the second controllable delay device.
13. The integrated circuit of claim 10 ,
wherein the first branch circuit includes a first output stage which, in response to a first binary value of the binary signal that is applied to the input node, connects the output node to a first logic potential via a first resistor,
wherein the second branch circuit includes a second output stage which, in response to a second binary value of a binary signal that is applied to the input node, connects the output node to a second logic potential via a second resistor; and
wherein the duty ratio control device is configured to set a signal propagation time of the binary signal from the input node to the first output stage relative to a signal propagation time of the binary signal from the input node to the second output stage.