Integrated semiconductor memory

1. An integrated semiconductor memory, comprising:

a multiplicity of externally programmable elements irreversibly programmable with a first or second programming state via a production unit during fabrication of the integrated semiconductor memory;

a read-out circuit for reading out the respective programming state of the programmable elements with an output terminal for generating a bit sequence of a first data record, wherein the read-out circuit reads out the respective programming state from a respective one of the programmable elements and generates the bit sequence of the first data record at the output terminal depending upon the respective programming state of the programmable elements; and

a decompression circuit with an input terminal for applying the bit sequence of the first data record and an output terminal for generating a bit sequence of a second data record, wherein the decompression circuit generates the bit sequence of the second data record based on a decompression method, so that the bit sequence of the second data record is longer than the bit sequence of the first data record.

2. The integrated semiconductor memory as claimed in claim 1 , wherein

the programmable elements are arranged in a continuous region of a chip area of the integrated semiconductor memory, the continuous region of the chip area with the programmable elements being arranged at least at a first distance from circuit components of the integrated semiconductor memory, the first distance selected such that the circuit components remain undamaged during programming of fuse elements by a laser pulse.

3. The integrated semiconductor memory as claimed in claim 2 , further comprising:

a memory cell array having memory cells, wherein the continuous region of the chip area with the programmable elements is at a second distance from the memory cell array than the remaining circuit components of the integrated semiconductor memory.

4. The integrated semiconductor memory as claimed in claim 1 , wherein the programmable elements are fuse elements.

5. The integrated semiconductor memory as claimed in claim 4 , wherein the fuse elements are programmed by a laser pulse.

6. The integrated semiconductor memory as claimed in claim 1 , wherein

the decompression circuit has a logic circuit,

the bit sequence of the first data record is fed to the logic circuit on the input side, and

the logic circuit generates the bit sequence of the second data record on the output side in the event of driving with the bit sequence of the first data record.

7. The integrated semiconductor memory as claimed in claim 6 , wherein

the logic circuit has a programming terminal for applying a programming signal, the logic circuit being programmed with a sequence control for decompression of the bit sequence of the first data record by applying the programming signal to the programming terminal.

8. The integrated semiconductor memory as claimed in claim 1 , further comprising:

a control circuit for controlling the integrated semiconductor memory with an input terminal for applying the bit sequence of the second data record, wherein

the bit sequence of the second data record is fed to the control circuit from the decompression circuit, and

upon initialization of the integrated semiconductor memory for a read and write access, the control circuit evaluates the bit sequence of the second data record from the decompression circuit and configures the integrated semiconductor memory for the read and write access based on the evaluated bit sequence of the second data record.

9. The integrated semiconductor memory as claimed in claim 1 , wherein

memory cells of a memory cell array are connected to a word line and to a respective bit line,

for read and write access to one of the memory cells, the respective word line is selected by a word line address and activated by a control circuit,

a redundant one of the word lines is activated by the control circuit in the event of read and write access to one of the memory cells connected to a defective one of the word lines,

the bit sequence of the second data record has a word line address, and

the control circuit evaluates the word line address in the bit sequence of the second data record and, instead of the word line associated with the word line address, activates the redundant one of the word lines for the read and write access.

10. A method for operating an integrated semiconductor memory, comprising:

providing an integrated semiconductor memory having externally programmable elements irreversibly programmable by a production unit during fabrication of the integrated semiconductor memory;

storing operating parameters of the integrated semiconductor memory in a compressed data format by programming of the programmable elements by the production unit during fabrication of the integrated semiconductor memory;

reading-out a respective programming state of the programmable elements upon each initialization of the integrated semiconductor memory;

generating a bit sequence of a first data record based on the programming state of the programmable elements respectively read out;

generating a bit sequence of a second data record by decompression of the bit sequence of the first data record;

driving a control circuit with the bit sequence of the second data record;

evaluating the bit sequence of the second data record by the control circuit; and

configuring the integrated semiconductor memory for read and write accesses by the control circuit based on the evaluated bit sequence of the second data record.

11. The method for operating the integrated semiconductor memory as claimed in claim 10 , further comprising:

providing the integrated semiconductor memory with a memory cell array, the memory cells each being arranged along word lines and bit lines, the word lines each assigned a word line address by which the respective word line is selected and a defective one of the word lines is replaced by a redundant one of the word lines, wherein the bit sequence of the second data record includes one of the respective word line addresses; and

activating the redundant one of the word lines by the control circuit, if the integrated semiconductor memory is driven by that one of the word line addresses assigned to that one of the defective word lines, and the bit sequence of the second data record includes that one of the word line addresses.