Combined receiver and latch

1. A combined receiver and latch circuit in a semiconductor memory device configured to receive an external clock signal, an external reference voltage and an external command signal, the circuit comprising:

first and second nodes each configured to be selectively precharged to a precharge voltage under the control of the clock signal;

a first control gate configured to receive the reference voltage;

a second control gate configured to receive the command signal; and

an output circuit coupled to the first and second nodes;

wherein the first and second nodes are alternatively discharged by the first and second control gates in response to the reference voltage and the command signal, and wherein the output circuit is configured to be latched upon the alternative discharge of the first and second node.

2. The combined circuit of claim 1 , wherein the first control gate is configured to control a first discharge path via the reference voltage and the second control gate is configured to control a second discharge path via the command signal.

3. The combined circuit of claim 1 further including a first transfer gate configured to receive the clock signal and coupled to the first node such that the first transfer gate selectively couples the first node to a precharge voltage in response to transitions of the clock signal and further including a second transfer gate configured to receive the clock signal and coupled to the second node such that the second transfer gate selectively couples the second node to the precharge voltage in response to transitions of the clock signal.

4. The combined circuit of claim 2 , wherein the output circuit is a flip flop having two NAND gates and including first and second inputs, wherein the first node is coupled to the first input of the output circuit and coupled to the first discharge path, wherein the second node is coupled to the second input of the output circuit and coupled to the second discharge path.

5. The combined circuit of claim 2 further including a third transfer gate in the first discharge path and configured to receive the clock signal such that the first discharge path is selectively opened in response to transitions of the clock signal and further including a fourth transfer gate in the second discharge path and configured to receive the clock signal such that the second discharge path is selectively opened in response to transitions of the clock signal.

6. The combined circuit of claim 5 further including first, second, third and fourth path gates, wherein the first and second path gates are connected in series between the first node and ground in the first discharge path, and wherein the third and fourth path gates are connected in series between the second node and ground in the second discharge path.

7. The combined circuit of claim 6 , wherein the first control gate is connected in parallel to the first and second path gates and wherein the second control gate is connected in parallel to the third and fourth path gates.

8. The combined circuit of claim 6 , wherein the first and second path gates are controlled by the voltage at the second node and wherein the third and fourth path gates are controlled by the voltage at the first node.

9. The combined circuit of claim 5 , further configured to be responsive to the clock signal such that the output circuit is configured to be latched upon both rising-edge transitions of the clock signal and upon falling-edge transitions of the clock signal.

10. The combined circuit of claim 2 , further including first and second latch gates, wherein the first latch gate is coupled between the precharge voltage and the first node and the first latch gate is controlled by the voltage at the second node, and wherein the second latch gate is coupled between the precharge voltage and the second node and the second latch gate is controlled by the voltage at the first node.

11. A combined circuit for receiving an clock signal, an reference voltage and an command signal, the circuit comprising:

a first control gate configured receive the reference voltage and to control a first discharge path;

a second control gate configured to receive the command signal and to control a second discharge path;

an output circuit with first and second inputs;

a first node coupled to the first input of the output circuit and coupled to the first discharge path;

a second node coupled to the second input of the output circuit and coupled to the second discharge path;

a first transfer gate configured to receive the clock signal and coupled to the first node such that the first transfer gate selectively couples the first node to a precharge voltage in response to transitions of the clock signal; and

a second transfer gate configured to receive the clock signal and coupled to the second node such that the second transfer gate selectively couples the second node to the precharge voltage in response to transitions of the clock signal;

wherein the output circuit is latched when the first and second nodes are alternately discharged.

12. The combined circuit of claim 11 , wherein the output circuit is a flip flop consisting of two NAND gates.

13. The combined circuit of claim 11 further including a third transfer gate in the first discharge path and configured to receive the clock signal such that the first discharge path is selectively opened in response to transitions of the clock signal and further including a fourth transfer gate in the second discharge path and configured to receive the clock signal such that the second discharge path is selectively opened in response to transitions of the clock signal.

14. The combined circuit of claim 13 further including first, second, third and fourth path gates, wherein the first and second path gates are connected in series between the first node and ground in the first discharge path, and wherein the third and fourth path gates are connected in series between the second node and ground in the second discharge path.

15. The combined circuit of claim 14 , wherein the first control gate is connected in parallel to the first and second path gates and wherein the second control gate is connected in parallel to the third and fourth path gates.

16. The combined circuit of claim 14 , wherein the first and second path gates are controlled by the voltage at the second node and wherein the third and fourth path gates are controlled by the voltage at the first node.

17. The combined circuit of claim 11 , further including first and second latch gates, wherein the first latch gate is coupled between the precharge voltage and the first node and the first latch gate is controlled by the voltage at the second node, and wherein the second latch gate is coupled between the precharge voltage and the second node and the second latch gate is controlled by the voltage at the first node.

18. A method for both receiving and for latching at the same time an external clock signal, an external reference voltage and an external command signal, the method comprising:

precharging first and second node to a precharge voltage when the clock signal is in a first state;

receiving relative magnitudes of the reference voltage and of the command signal;

discharging the first node and holding the precharge voltage at the second node when the magnitude of the reference voltage is greater than the magnitude of the command signal;

discharging the second node and holding the precharge voltage at the first node when the magnitude of the command signal is greater than the magnitude of the reference voltage; and

toggling an output circuit when the voltage at one of the first and second nodes is discharged and the voltage and the other of the first and second nodes is the precharge voltage.

19. The method of claim 18 applied to a receiver and latch circuit in a semiconductor memory device that is configured to receive the external clock signal, the external reference voltage and the external command signal.

20. The method of claim 18 , wherein a first control gate is configured receive the reference voltage and to control discharging the first node, wherein a second control gate is configured to receive the command signal and to control discharging the second, wherein a first transfer gate is configured to receive the clock signal and coupled to the first node such that the first transfer gate selectively precharges the first node, and wherein a second transfer gate is configured to receive the clock signal and coupled to the second node such that the second transfer gate selectively precharges the second node.