Memory component having a novel arrangement of the bit lines
View Patent ↗A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.
1. A memory component, comprising:
a plurality of bit lines arranged in a plurality of columns;
a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns;
a plurality of memory cells are disposed at respective intersections of each bit line and each word line; and
a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least three adjacent sense amplifiers and a corresponding number of adjacent bit lines, and wherein there are no intervening bit lines at any point between the adjacent bit lines along their respective lengths; and
wherein the bit lines between a first and second adjacent rows of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the second row.
2. A memory component, comprising:
a plurality of bit lines arranged in a plurality of columns;
a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns;
a plurality of memory cells are disposed at respective intersections of each bit line and each word line; and
a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least three adjacent sense amplifiers and a corresponding number of adjacent bit lines, and wherein there are no intervening bit lines at any point between the adjacent bit lines along their respective lengths;
wherein the bit lines between a first and second adjacent rows of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the second row; and
wherein the bit lines between the first row and a third row of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the third row.
3. A memory component, comprising:
a plurality of bit lines arranged in a plurality of columns;
a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns;
a plurality of memory cells are disposed at respective intersections of each bit line and each word line; and
a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least three adjacent sense amplifiers and a corresponding number of adjacent bit lines, and wherein there are no intervening bit lines at any point between the adjacent bit lines along their respective lengths;
wherein the bit lines between a first and second adjacent rows of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the second row;
wherein the bit lines between the first row and a third row of sense amplifiers are arrangd into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the third row; and
wherein each sense amplifier of the first row is connected to one respective bit line between the first row and the second row of sense amplifiers and to one respective bit line between the first row and the third row of sense amplifiers.
4. A memory component, comprising:
a plurality of bit lines arranged in a plurality of columns;
a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns;
a plurality of memory cells are disposed at respective intersections of each bit line and each word line; and
a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least three adjacent sense amplifiers and a corresponding number of adjacent bit lines, and wherein there are no intervening bit lines at any point between the adjacent bit lines along their respective lengths;
wherein the bit lines between a first and second adjacent rows of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the second row;
wherein the bit lines between the first row and a third row of sense amplifiers are arranged into groups, each group comprising at least three adjacent bit lines, and connected in an interleaved arrangement, wherein the groups of bit lines are connected in an alternating manner to respective adjacent sense amplifiers of the first row and respective adjacent sense amplifiers of the third row;
wherein each sense amplifier of the first row is connected to one respective bit line between the first row and the second row of sense amplifiers and to one respective bit line between the first row and the third row of sense amplifiers; and
wherein the respective bit lines which are connected to the sense amplifiers in the first row are respectively arranged directly adjacent to at most one bit line connected to one sense amplifier arranged in one of the second row and the third row.