Circuit for data bit inversion

1. An electric circuit for inverting a data bit of a data burst read out from a memory module, comprising:

a buffer for buffering a data burst being comprised of at least two data words, each comprising a specific number of data bits;

a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously an associated present data word of said data words buffered in said buffer with a reference data word and generating an inversion flag, if the number of different data bits of said data word present at said decoder and said reference data word exceeds half said specific number; said reference data word being a data word of said data words buffered in said buffer and neighbouring said present data word;

a correction device for generating a corrected inversion flag for a specific decoder of said decoders by inverting or not inverting said inversion flag of said specific decoder dependent on said inversion flag generated by said specific decoder and said inversion flags generated by the remaining decoders of said decoders; and

an inversion device comprised of a plurality of inverters, each inverting or not inverting said present word of an associated of said decoders dependent on said corrected inversion flag of said associated decoder.

2. The electric circuit of claim 1 , comprising a parallel-to-serial converter for converting said data words output by said inversion device and said associated corrected inversion flags in a parallel-to-serial fashion in order to output the result of said conversion from said memory module as a further data burst.

3. The electric circuit of claim 1 , wherein each of said inverters comprise a plurality of XOR gates.

4. The electric circuit of claim 1 , wherein each of said decoders comprises a logic circuit comparing said first and second data words in a bitwise fashion.

5. The electric circuit of claim 4 , wherein said logic circuit comprises a plurality of XOR gates.

6. The electric circuit of claim 1 , wherein each of said decoders comprises a counter determining the number of said different data bits between said present data word and said reference data word.

7. The electric circuit of claim 6 , wherein each of said decoders comprises a comparator comparing said number determined by said counter with half said specific number.

8. The electric circuit of claim 7 , wherein said comparator generates a logically high inversion flag when said number determined by said counter exceed half said specific number.

9. The electric circuit of claim 1 , wherein said correction device is a separate electric circuit connected downstream of said decoder device.

10. The electric circuit of claim 1 , wherein said correction device is integrated in said decoder device.

11. The electric circuit of claim 10 , wherein said integrated correction device comprises of a plurality of correction circuits, each being included in an associated of said decoders.

12. The electric circuit of claim 11 , wherein a specific of said correction circuits is formed by a logic circuit correcting said inversion flag generated by said comparator of said decoder associated with said specific correction circuit dependent on said inversion flags generated by the remaining of said comparators in order to generate said corrected inversion flag.

13. The electric circuit of claim 11 , wherein a specific of said correction circuits is formed by a memory from which said corrected inversion flag of said decoder associated with said specific correction circuit is read out as a function of said inversion flag generated by said specific comparator and as a function of said inversion flags generated the remaining of said comparators.

14. The electric circuit of claim 12 , wherein said corrected inversion flag drives a multiplexer of said decoder which outputs said data word applied to said decoder in a direct or inverted fashion.

15. The electric circuit of claim 1 , wherein each of said data bursts comprises four data words.

16. The electric circuit of claim 1 , wherein each of said data words comprises 8 bits.

17. The electric circuit of claim 1 , wherein each of said decoders is connected to a gap-detection device ascertaining whether a gap exists between two of said data bursts in order to generate a control signal for a multiplexer.

18. The electric circuit of claim 17 , wherein, when a gap exists between two of said data bursts, said gap-detection device drives said multiplexer in such a way that a predetermined data word is switched through for the purpose of bitwise comparing it with said present data word, and, when no gap exists between two of said data bursts, the gap-detection device drives said multiplexer in such a way that said reference data word is switched through for the purpose of bitwise comparing it with said present data word.

19. The electric circuit of claim 17 , wherein two separate of said decoders are connected downstream of said multiplexer driven by said control signal generated by said gap-detection device; a first decoder of said two separate decoders comparing said present data word with said reference data word in bitwise fashion in order to generate a first inversion flag; a second decoder of said two separate decoders comparing said present data word with a predetermined data word in order to generate a second inversion flag; and said multiplexer switching said first inversion flag or said second inversion flag through to said correction device dependent on said control signal.