Circuit for producing a data bit inversion flag

1. A circuit for producing a data bit inversion flag, comprising:

a first summed-current production unit for producing a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent data words in a data burst;

a second summed-current production unit for producing a second summed current, whose amplitude is proportional to the number of identical data bits in said two adjacent data words; and

a current comparator comparing said first summed current with said second summed current and producing a data bit inversion flag if said first summed current is greater than said second summed current.

2. The circuit of claim 1 , wherein said two summed-current production units each comprise transistors connected in parallel; said transistor switching on the basis of said data bits.

3. The circuit of claim 2 , wherein said two complementary transistors in said first inverter stage are connected to one another at a first node.

4. The circuit of claim 3 , wherein said transistors in said first inverter stage are MOS or NMOS field-effect transistors.

5. The circuit of claim 3 , wherein said two complementary transistors in said second inverter stage are connected to one another at a second node.

6. The circuit of claim 5 , wherein said first node and said second node are held at a prescribed supply potential in a deactivated state of said circuit by means of a PULL-UP circuit.

7. The circuit of claim 6 , wherein said PULL-UP circuit comprises transistors which are switched on the basis of a start control signal.

8. The circuit of claim 7 , wherein said transistors of said PULL-UP circuit are MOS field-effect transistors or MOS field-effect transistors.

9. The circuit of claim 3 , wherein said data bit inversion flag is tapped off for output at said first node.

10. The circuit of claim 3 , wherein said two complementary transistors in said second inverter stage are connected to one another at a second node and said first node and said second node are connected to a NAND gate for producing a Ready indicator signal.

11. The circuit of claim 2 , wherein said transistors in said second inverter stage are MOS or NMOS field-effect transistors.

12. The circuit of claim 1 , wherein said two adjacent data words each have an added supplementary data bit with a fixed logic value so that the number of said data bits within a data word is always uneven.

13. The circuit of claim 1 , wherein said current comparator is formed by a differential amplifier.

14. The circuit of claim 1 , wherein said current comparator is clocked by a data clock signal.

15. The circuit of claim 14 , wherein said circuit can be activated by a start control signal which is formed by said data clock signal.

16. The circuit of claim 15 , wherein said first summed-current production unit and said second summed-current production unit are connected to one another at a fifth node which can be connected by a transistor to, a prescribed supply voltage potential on the basis of said start control signal.

17. The circuit of claim 16 , wherein said transistor which can connect said fifth node to said prescribed supply voltage potential are MOS field-effect transistors or MOS field-effect transistors.

18. The circuit of claim 1 , wherein said current comparator comprises two inverter stages each having two complementary transistors.

19. The circuit of claim 18 , wherein said transistors of said current comparator are MOS or NMOS field-effect transistors.

20. The circuit of claim 1 , wherein said current comparator is connected to said first current production unit at a third node and to said second current production unit at a fourth node.

21. The circuit of claim 20 , wherein said third node and said fourth node are shorted via at least one further transistor when said circuit has been deactivated.

22. The circuit of claim 1 , wherein said first summed-current production unit and said second summed-current production unit are connected to one another at a fifth node.

23. The circuit of claim 1 , wherein said data bit inversion flag actuates a multiplexer which takes said data bit inversion flag as a basis for switching through the present of said two adjacent data words in inverted or uninverted form.

24. A method for producing a data bit inversion flag, comprising the steps of:

producing a first summed current, whose amplitude is proportional to the number of different data bits in two adjacent words in a data burst;

producing a second summed current, whose amplitude is proportional to the number of identical data bits in said two adjacent data words in a data burst;

comparing said first summed current with said second summed current; and

setting a data bit inversion flag to a logic value if said first summed current is greater than said second summed current.