Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)

1. Dual In Line Memory Module having a predetermined number of memory chips mounted on a printed circuit board wherein each memory chip comprises a predetermined number of stacked memory dies which are selectable by a memory rank selection signal, wherein the memory rank selection signal is generated by a memory rank decoder in response to external selection signals applied to the Dual In Line Memory Module,

wherein the memory chips are selectable by memory chip select signals, and

wherein the predetermined number of stacked memory dies is greater than the number of the external selection signals applied to the Dual In Line Memory Module.

2. Dual In Line Memory Module according to claim 1 wherein each memory chip comprises an integrated memory rank decoder.

3. Dual In Line Memory Module according to claim 1 wherein the memory chips are mounted on both sides of the printed circuit board so that the number of memory ranks of said Dual In Line Memory Module is twice the number of stacked memory dies within each memory chip.

4. Dual In Line Memory Module according to claim 1 wherein the Dual In Line Memory Module is a registered Dual In Line Memory Module having a command and address buffer chip for buffering external command and address signals applied to the Dual In Line Memory Module.

5. Dual In Line Memory Module according to claim 4 wherein the command and address buffer chip further buffers an external clock signal applied to the Dual In Line Memory Module.

6. Dual In Line Memory Module according to claim 4 wherein the command and address buffer chip is connected by a command and address bus to all memory chips mounted on the printed circuit board.

7. Dual In Line Memory Module according to claim 4 wherein the memory rank decoder is integrated in said command and address buffer chip.

8. Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module having a predetermined number of memory chips mounted on a printed circuit board, wherein each memory chip comprises a predetermined number of stacked memory dies which are selectable by a memory rank selection signal, wherein the memory rank decoder generates the memory rank selection signal in response to external selection signals applied to the dual inline module,

wherein the memory chips are selectable by memory chip select signals, and

wherein the predetermined number of stacked memory dies is greater than the number of the external selection signals applied to the Dual In Line Memory Module.

9. Memory Rank Decoder according to claim 8 , wherein the Memory Rank Decoder is integrated in a command and address buffer chip which is provided for buffering external command and address signals applied to the dual inline memory module.

10. Memory Rank Decoder according to claim 8 , wherein the Memory Rank Decoder is integrated in each memory chip of the dual inline memory module.

11. Memory Rank Decoder according to claim 8 , wherein the memory chip is a DRAM memory chip.