Phase change memory cell with high read margin at low power operation

1. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode laterally surrounded by insulation material, the first electrode having an exposed upper surface aligned with an exposed upper surface of the insulation material;

depositing a phase-change material layer adjacent the preprocessed wafer such that the phase-change material layer directly contacts the entire exposed upper surface of the first electrode;

depositing an electrode material layer adjacent the phase-change material layer;

etching the phase-change material layer and the electrode material layer to form a second electrode and a storage location such that sidewalls of the second electrode and the storage location are aligned; and

depositing isolation material adjacent the storage location, the isolation material having a thermal conductivity between 0.1 and 0.8 W/mK.

2. The method of claim 1 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer having a first electrode comprising a contact material deposited adjacent a metallic plug.

3. The method of claim 1 , wherein etching the phase-change material layer and the electrode material layer comprises etching the phase-change material layer and the electrode material layer based on a sublithographic mask layer.

4. The method of claim 1 , further comprising:

depositing a diffusion barrier surrounding the storage location for preventing diffusion of the phase-change material into the isolation material.

5. The method of claim 4 , wherein depositing the diffusion barrier comprises depositing SiN.

6. The method of claim 1 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising a tungsten plug.

7. The method of claim 1 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising a copper plug.

8. The method of claim 1 , wherein depositing the phase-change material layer comprises depositing a chalcogenide material layer.

9. The method of claim 1 , wherein depositing the electrode material layer comprises depositing one of TiN and TaN.

10. The method of claim 1 , further comprising:

depositing insulation material adjacent the second electrode.

11. The method of claim 10 , wherein depositing insulation material comprises depositing one of SiO 2 and fluorinated silica glass.

12. A method for fabricating a memory cell device, the method comprising:

providing a preprocessed wafer having a first electrode laterally surrounded by insulation material, the first electrode having an exposed upper surface alianed with an exposed upper surface of the insulation material;

depositing an isolation material layer adjacent the preprocessed wafer such that the isolation material layer directly contacts the entire exposed upper surface of the first electrode, the isolation material having a thermal conductivity between 0.1 and 0.8 W/mK;

depositing a stop layer adjacent the isolation material layer;

depositing a sacrificial layer adjacent the stop layer;

etching the sacrificial layer to the stop layer to form a tapered via above the first electrode;

etching the stop layer and the isolation layer at a bottom of the tapered via to form an extended via;

removing the sacrificial layer;

depositing phase-change material in the extended via; and

fabricating a second electrode adjacent the phase-change material.

13. The method of claim 12 , further comprising:

depositing a diffusion barrier adjacent the isolation layer to prevent diffusion of the phase-change material into the isolation material.

14. The method of claim 13 , wherein depositing the diffusion barrier comprises depositing SiN.

15. The method of claim 12 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising a tungsten plug.

16. The method of claim 12 , wherein providing the preprocessed wafer comprises providing a preprocessed wafer comprising a copper plug.

17. The method of claim 12 , wherein depositing the stop layer comprises depositing a SiN layer.

18. The method of claim 12 , wherein depositing the sacrificial layer comprises depositing a SiO 2 layer.

19. The method of claim 12 , wherein depositing phase-change material comprises depositing a chalcogenide material layer.

20. The method of claim 12 , further comprising:

depositing insulation material adjacent the second electrode and the storage location.

21. The method of claim 20 , wherein depositing insulation material comprises depositing one of SiO 2 and fluorinated silica glass.

22. A method for fabricating an integrated circuit having a memory cell, the method comprising:

providing a preprocessed wafer including a first electrode laterally surrounded by insulation material, the first electrode having an exposed upper surface aligned with an exposed upper surface of the insulation material;

depositing a resistivity changing material layer over the preprocessed wafer such that the resistivity changing material layer directly contacts the entire exposed tipper surface of the first electrode;

depositing an electrode material layer over the resistivity changing material layer; etching the resistivity changing material layer and the electrode material layer to expose portions of the first electrode to provide a storage location and a second electrode;

depositing a diffusion barrier material layer over exposed portions of the second electrode, the storage location, and the first electrode;

depositing an isolation material layer over the diffusion barrier material layer, the isolation material having a thermal conductivity between 0.1 and 0.8 W/mK; and

planarizing the isolation material layer and the diffusion barrier material layer to expose the second electrode.