Memory with resistance memory cell and evaluation circuit
View Patent ↗A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitor has a reference memory cell with a reference resistor which is connected between the ground terminal and a reference capacitor, in which case, during the reading operation of the memory cell, the memory cell and the reference memory cell are switched on in order to charge or discharge the capacitor and the reference capacitor, and an evaluation device evaluates the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell.
1. A memory circuit, comprising:
a memory cell having a resistance memory element that can be switched between a high-resistance state and a low-resistance state by means of electrical pulses and being connected between a ground terminal and a capacitor;
an evaluation device configured to assess the difference between the electrical potentials of the capacitor and a reference capacitor; and
a reference memory cell with a reference resistor and connected between the ground terminal and the reference capacitor; the memory cell and the reference memory cell being switched on during the reading operation in order to charge the capacitor and the reference capacitor to a read voltage or in order to discharge the capacitor and the reference capacitor which have been precharged to the read voltage, and the evaluation device assessing the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell, wherein the reference resistor meets the following condition:
R
REF
=
R
ON
·
ln
F
ln
(
F
+
1
)
-
ln
2
where
F
=
exp
(
-
t
R
ON
·
C
BL
)
C BL being one of the capacitance and the reference capacitance, R ON being the resistance of the memory cell in the low-resistance state, and t being the evaluation instant.
2. The memory circuit as claimed in claim 1 , wherein the memory cells each have a selection transistor, which is arranged in series with the resistance memory element and is switched via an associated word line.
3. The memory circuit as claimed in claim 1 , wherein the reference resistor is formed from a series circuit of resistance memory elements.
4. The memory circuit as claimed in claim 3 , further comprising:
a programming circuit in order to activate the resistance memory elements that form the reference resistor.
5. The memory circuit as claimed in claim 1 , wherein the capacitor and the reference capacitor are formed by a line pair comprising a bit line and a complementary bit line.
6. The memory circuit as claimed in claim 5 , further comprising:
a multiplicity of memory cells each having a respective reference resistor and each connected to the bit line and to the complementary bit line in parallel, wherein when a memory cell of the multiplicity of memory cells is connected to the bit line is switched on, the reference resistor on the complementary bit line is simultaneously switched on, and when a memory cell of the multiplicity of memory cells connected to the complementary bit line is switched on, the reference resistor on the bit line is simultaneously switched on.
7. A memory circuit comprising:
a memory cell having a resistance memory element that can be switched between a high-resistance state and a low-resistance state by means of electrical pulses and being connected between a ground terminal and a capacitor;
an evaluation device configured to assess the difference between the electrical potentials of the capacitor and a reference capacitor;
a reference memory cell with a reference resistor and connected between the ground terminal and the reference capacitor; the memory cell and the reference memory cell being switched on during the reading operation in order to charge the capacitor and the reference capacitor to a read voltage or in order to discharge the capacitor and the reference capacitor which have been precharged to the read voltage, and the evaluation device assessing the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell, the reference resistor of the reference memory cell being formed from a series circuit including at least two resistance memory elements; and
a selection transistor of the reference memory cell connected upstream of the series circuit of at least two resistance memory elements that forms the reference resistor, wherein a selection transistor of the memory cell is connected upstream of the resistance memory element of the memory cell, a channel length of the selection transistor of the reference memory cell corresponding to a channel length of the selection transistors of the memory cells multiplied by the number of resistance memory elements of the reference memory cell connected in series.
8. The memory circuit as claimed in claim 7 , further comprising:
a programming circuit in order to activate the resistance memory elements that form the reference resistor.
9. The memory circuit as claimed in claim 8 , wherein the reference resistor meets the following condition:
R
REF
=
R
ON
·
ln
F
ln
(
F
+
1
)
-
ln
2
where
F
=
exp
(
-
t
R
ON
·
C
BL
)
C BL being one of the capacitance and the reference capacitance, R ON being the resistance of the memory cell in the low-resistance state, and t being the evaluation instant.
10. The memory circuit as claimed in claim 7 , wherein the reference resistor meets the following condition:
R
REF
=
R
ON
·
ln
F
ln
(
F
+
1
)
-
ln
2
where
F
=
exp
(
-
t
R
ON
·
C
BL
)
C BL being one of the capacitance and the reference capacitance, R ON being the resistance of the memory cell in the low-resistance state, and t being the evaluation instant.
11. A memory circuit, comprising:
a memory cell having a resistance memory element that can be switched between a high-resistance state and a low-resistance state by means of electrical pulses and being connected between a ground terminal and a capacitor;
an evaluation device configured to assess the difference between the electrical potentials of the capacitor and a reference capacitor; and
a reference memory cell with a reference resistor and connected between the ground terminal and the reference capacitor, the memory cell and the reference memory cell being switched on during the reading operation in order to charge the capacitor and the reference capacitor to a read voltage or in order to discharge the capacitor and the reference capacitor which have been precharged to the read voltage, and the evaluation device assessing the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell;
the reference resistor of the reference memory cell being configured such that, at the predetermined instant, a reference voltage of the reference memory circuit lies between a voltage of the memory cell corresponding to the low-resistance state and a voltage of the memory cell corresponding to the high-resistance state;
wherein the reference resistor of the reference memory cell meets the following condition;
R
REF
=
R
ON
·
ln
F
ln
(
F
+
1
)
-
ln
2
where
F
=
exp
(
-
t
R
ON
·
C
BL
)
C BL being one of the capacitance and the reference capacitance, R ON being the resistance of the memory cell in the low-resistance state, and t being the evaluation instant.