Duty cycle corrector
View Patent ↗A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.
1. A duty cycle corrector, comprising:
a first circuit;
a second circuit; and
a third circuit configured to reach a threshold value in response to a charge flow that is regulated by the first circuit and the second circuit;
wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal to provide a first charge flow and the second circuit is configured to change the charge flow at a second transition of the clock signal to provide the first charge flow, and the first circuit and the second circuit are configured to change the charge flow to provide a second charge flow opposite to the first charge flow in response to reaching the threshold value.
2. The duty cycle corrector of claim 1 , wherein the first circuit is configured to increase the first charge flow at the first transition and the second circuit is configured to increase the first charge flow at the second transition.
3. The duty cycle corrector of claim 1 , wherein the first circuit is configured to decrease the first charge flow in response to reaching the threshold value and the second circuit is configured to decrease the first charge flow in response to reaching the threshold value.
4. The duty cycle corrector of claim 1 , wherein the third circuit comprises a capacitor and the first charge flow discharges the capacitor, wherein the first circuit is configured to increase the first charge flow away from the capacitor at the first transition and the second circuit is configured to increase the first charge flow away from the capacitor at the second transition.
5. The duty cycle corrector of claim 4 , wherein the first circuit is configured to decrease the first charge flow away from the capacitor in response to reaching the threshold value and the second circuit is configured to decrease the first charge flow away from the capacitor in response to reaching the threshold value.
6. The duty cycle corrector of claim 1 , wherein the third circuit comprises:
a capacitor that receives the first charge flow and the second charge flow, wherein the first charge flow charges the capacitor and the second charge flow discharges the capacitor.
7. The duty cycle corrector of claim 6 , wherein the first charge flow provided to the capacitor between the first transition and the second transition of the clock signal charges the capacitor at a first rate and the first charge flow provided to the capacitor after the second transition of the clock signal charges the capacitor at a second rate that is higher than the first rate.