Storage capacitor and method of manufacturing a storage capacitor
View Patent ↗An integrated circuit including a storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.
1. An integrated circuit comprising a storage capacitor, comprising:
a storage electrode comprising a first section and a second section,
a first counter electrode comprising a first portion adjacent to the first section of the storage electrode, and a second portion, which does not extend along the storage electrode;
a first dielectric layer being disposed between the first portion of the first counter electrode and the storage electrode;
a second counter electrode comprising a first portion adjacent to a second section of the storage electrode and a second portion which does not extend along the storage electrode; and
a second dielectric layer being disposed between the first portion of the second counter electrode and the storage electrode; wherein
the first and the second counter electrodes are electrically connected with each other, the first counter electrode is disposed in a first layer and the second counter electrode is disposed in a second layer above the first layer, and the first and second dielectric layers are not connected with each other.
2. The integrated circuit of claim 1 , wherein
the first portion of the first counter electrode extends in a first direction;
the first portion of the second counter electrode extends in a second direction; and
the first direction is equal to the second direction.
3. The integrated circuit of claim 1 , wherein at least one of the second portion of the first counter electrode and the second portion of the second counter electrode is parallel with the substrate surface.
4. The integrated circuit of claim 1 , wherein the first portion of at least one of the first and second counter electrodes is parallel with the storage electrode.
5. The integrated circuit of claim 1 , further comprising
n further counter electrodes, disposed in a (n+2)-th layer above the (n+1)-th layer respectively, each of the n counter electrodes comprising a first portion adjacent to a (n+2)-th section of the storage electrode, and a second portion which does not extend along the storage electrode; and
a (n+2)-th dielectric layer being disposed between the first portion of the (n+2)-th counter electrode and the storage electrode;
wherein all of the first, second and (n+2)-th counter electrodes are electrically connected with each other.
6. The integrated circuit of claim 1 , wherein the second portion of individual ones of the counter electrodes is disposed closer to the substrate surface than the first portion of the corresponding one of the counter electrodes, respectively.
7. The integrated circuit of claim 1 , wherein the storage electrode is at least partially formed above a substrate surface.
8. The integrated circuit of claim 1 , wherein the storage electrode is disposed at an angle of 89 to 91 degrees with respect to a substrate surface, above which the storage capacitor is formed at least partially.
9. The integrated circuit of claim 1 , wherein the second portion of at least one of the counter electrodes is parallel with a substrate surface, above which the storage capacitor is formed at least partially.
10. The integrated circuit of claim 5 , wherein at least one of the first portions of any of the counter electrodes is parallel with the storage electrode.
11. An integrated circuit comprising a memory cell array comprising:
transistors and storage capacitors, individual ones of the storage capacitors comprising respectively:
a storage electrode comprising a first section and a second section;
a first counter electrode comprising a first portion adjacent to the first section of the storage electrode, and a second portion, which does not extend along the storage electrode;
a first dielectric layer being disposed between the first portion of the first counter electrode and the storage electrode;
a second counter electrode comprising a first portion adjacent to a second section of the storage electrode and a second portion which does not extend along the storage electrode; and
a second dielectric layer being disposed between the first portion of the second counter electrode and the storage electrode, wherein
the first and the second counter electrodes are electrically connected with each other, the first counter electrode is disposed in a first layer and the second counter electrode is disposed in a second layer above the first layer, and the first and second dielectric layers are not connected with each other.
12. An integrated circuit comprising a storage capacitor, comprising:
a storage electrode comprising a first section and a second section;
a first counter electrode comprising a first portion adjacent to the first section of the storage electrode, and a second portion, which does not extend along the storage electrode;
a first dielectric layer being disposed between the first portion of the first counter electrode and the storage electrode;
a second counter electrode comprising a first portion adjacent to a second section of the storage electrode, and a second portion which does not extend along the storage electrode; and
a second dielectric layer being disposed between the first portion of the second counter electrode and the storage electrode, wherein the first and the second counter electrodes are electrically connected with each other and the first and the second dielectric layers are not connected with each other.
13. The integrated circuit of claim 12 , wherein
the first portion of the first counter electrode extends in a first direction;
the first portion of the second counter electrode extends in a second direction; and
the first direction is equal to the second direction.
14. The integrated circuit of claim 12 , wherein at least one of the second portions of the first counter electrode and the second portion of the second counter electrode is parallel with the substrate surface.
15. The integrated circuit of claim 12 , wherein the first portion of at least one of the first and second counter electrodes is parallel with the storage electrode.
16. The integrated circuit of claim 12 , further comprising
n further counter electrodes, disposed in a (n+2)-th layer above the (n+1)-th layer respectively, each of the n counter electrodes comprising a first portion adjacent to a (n+2)-th section of the storage electrode, and a second portion which does not extend along the storage electrode; and
a (n+2)-th dielectric layer being disposed between the first portion of the (n+2)-th counter electrode and the storage electrode;
wherein all of the first, second and (n+2)-th counter electrodes are electrically connected with each other.
17. The integrated circuit of claim 12 , wherein the second portion of individual ones of the counter electrodes, is disposed closer to the substrate surface than the first portion of the corresponding one of the counter electrodes, respectively.
18. The integrated circuit of claim 12 , wherein the storage electrode is at least partially formed above a substrate surface.
19. The integrated circuit of claim 1 , wherein the storage electrode is disposed at an angle of 89 to 91 degrees with respect to the substrate surface, above which the storage capacitor is formed at least partially .
20. The integrated circuit of claim 12 , wherein the second portion of at least one of the counter electrodes is parallel with a substrate surface, above which the storage capacitor is formed at least partially.
21. The integrated circuit of claim 16 , wherein at least one of the first portions of any of the counter electrodes is parallel with the storage electrode.
22. An integrated circuit comprising a memory cell array comprising
transistors and storage capacitors, individual ones of the storage capacitors comprising respectively:
a storage electrode comprising a first section and a second section;
a first counter electrode comprising a first portion adjacent to the first section of the storage electrode, and a second portion, which does not extend along the storage electrode;
a first dielectric layer being disposed between the first portion of the first counter electrode and the storage electrode;
a second counter electrode comprising a first portion adjacent to a second section of the storage electrode, and a second portion which does not extend along the storage electrode; and
a second dielectric layer being disposed between the first portion of the second counter electrode and the storage electrode, wherein the first and the second counter electrodes are electrically connected with each other, and the first and the second dielectric layers are not connected with each other.