IP Library Granted Patent US 7,332,443
Granted Patent B2
US 7,332,443 · App. 11/084,728 · Granted Feb 19, 2008

Method for fabricating a semiconductor device

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Quick Facts
Patent No.
US 7,332,443
App. No.
11/084,728
Granted
Feb 19, 2008
Kind
B2
Abstract

The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the device, germanium atoms are implanted into a surface of a semiconductor substrate such that a germanium-containing layer inside the semiconductor substrate is formed. Then, the surface of the semiconductor surface is oxidized down to and including the upper part of the germanium-containing layer, thereby pushing the implanted germanium atoms from the surface down into the semiconductor substrate and thereby enhancing the germanium concentration inside the remaining germanium-containing layer and forming a layer with enhanced germanium concentration inside the semiconductor substrate. The fabrication of the semiconductor device is concluded such that the active region of the device is placed at least partly within the layer with enhanced germanium concentration.

Claims (25)

1. A method for fabricating a transistor device having a source region, a drain region and a channel region the method comprising:

implanting germanium into a surface of a semiconductor body and forming a germanium-containing layer inside the semiconductor body having a first germanium concentration;

oxidizing the surface of the semiconductor surface down to and including an upper part of the germanium-containing layer, thereby pushing the implanted germanium atoms from the surface down into the semiconductor body and thereby enhancing the germanium concentration inside the remaining germanium-containing layer and forming a layer with an enhanced or a second germanium concentration inside the semiconductor body where said transistor is to be formed, and wherein the thickness of an oxide grown during said oxidation step is reduced and the remaining oxide layer with reduced thickness is used as a gate oxide for the transistor; and

concluding the fabrication of the transistor device such that the source region, the drain region and the channel region of the transistor device is within the layer with enhanced germanium concentration such that each of the source region, the drain region and the channel region have said second germanium concentration.

2. The method according to claim 1 , wherein the semiconductor body comprises a silicon substrate.

3. The method according to claim 1 , wherein a field effect transistor is fabricated as the transistor device.

4. The method according to claim 1 , wherein the oxidation step is carried out at a temperature between about 800 and 1200 degrees Celsius.

5. The method according to claim 1 , wherein the oxidation step is carried out such that the layer with enhanced germanium concentration contains at least 20% germanium.

6. The method according to claim 1 , wherein germanium is implanted by applying an implant dose of at least 10 15 cm −2 .

7. The method according to claim 6 , wherein germanium is implanted by applying an implant dose of at least 10 16 cm −2 .

8. The method according to claim 1 , wherein the thickness of the oxide is reduced by etching or polishing the oxide.

9. A method for fabricating a transistor device having a source region, a drain region and a channel region the method comprising:

implanting germanium into a surface of a semiconductor body and forming a germanium-containing layer inside the semiconductor body having a first germanium concentration;

oxidizing the surface of the semiconductor body down to and including an upper part of the germanium-containing layer, thereby pushing the implanted germanium atoms from the surface down into the semiconductor body and thereby enhancing the germanium concentration inside the remaining germanium-containing layer and forming a layer with an enhanced or second germanium concentration inside the semiconductor body;

completely removing an oxide grown during said oxidizing step;

re-oxidizing the surface of the remaining semiconductor substrate during a second oxidation step and forming a second oxide layer, thereby pushing implanted germanium atoms further down into the semiconductor body to further enhancing the germanium concentration inside another germanium containing layer, such that said another layer has a third germanium concentration; and

concluding the fabrication of the transistor device such that the source region, the drain region and the channel region of the transistor device is within the another germanium containing layer, such that each of the source region, the drain region and the channel region have said third germanium concentration.

10. The method according to claim 9 , wherein the second oxide layer is used as an insulation layer on top of the active region.

11. The method according to claim 10 , wherein the semiconductor substrate is a silicon substrate.

12. The method according to claim 9 , wherein a field effect transistor is fabricated as the semiconductor device.

13. The method according to claim 9 , wherein the oxidation step is carried out at a temperature between about 800 and 1200 degrees Celsius.

14. The method according to claim 9 , wherein the oxidation step is carried out such that the layer with enhanced germanium concentration contains at least 20% germanium.

15. The method according to claim 14 , wherein germanium is implanted by applying an implant dose of at least 10 −15 cm −2 .

16. The method according to claim 15 , wherein germanium is implanted by applying an implant dose of at least 10 −16 cm −2 .

17. The method according to claim 9 , wherein the oxide produced during the first oxidation step is removed by etching or polishing.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036908/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →