Phase change memory cell with high read margin at low power operation

1. A memory cell device comprising:

a first electrode;

phase-change material adjacent the first electrode;

a second electrode adjacent the phase-change material;

a diffusion barrier adjacent the phase-change material; and

isolation material adjacent the diffusion barrier for thermally isolating the phase-change material,

wherein the diffusion barrier prevents diffusion of the phase-change material into the isolation materia 1 ,

wherein the isolation material comprises a dielectric material that limits the heat leakage from the phase change material, and

wherein the dielectric material comprises a porous oxide film having a thermal conductivity between 0.1 and 0.8 W/mk.

2. The memory cell device of claim 1 , wherein the phase-change material comprises a chalcogenide.

3. The memory cell device of claim 2 , wherein the phase-change material comprises GeSbTe.

4. The memory cell device of claim 1 , wherein the diffusion barrier comprises SiN.

5. The memory cell device of claim 1 , wherein the phase-change material comprises a chalcogen-free material.

6. A memory cell device comprising:

a first electrode;

phase-change material adjacent the first electrode;

a second electrode adjacent the phase-change material;

isolation material for thermally isolating the phase-change material; and

a diffusion barrier for preventing diffusion of the phase-change material into the isolation material,

wherein the isolation material comprises a dielectric porous oxide film having a thermal conductivity between 0.1 and 0.8 W/mk.

7. The memory cell device of claim 6 , wherein the phase-change material comprises a chalcogenide.

8. The memory cell device of claim 7 , wherein the phase-change material comprises GeSbTe.

9. The memory cell device of claim 6 , wherein the phase-change material comprises a chalcogen-free material.

10. The memory cell device of claim 6 , wherein the diffusion barrier comprises SiN.