Patent Assignment
Reel/Frame 036539/0196
Assignment of Assignor's Interest
Recorded: 2015-09-03
Pages: 11
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(147)
Sense Amplifier
System and Method for Determining Yield Impact for Semiconductor Devices
Light Absorption Layer for Laser Blown Fuses
Patent:
6,323,067 →
Application:
09/238,543 →
Use of Dummy Poly Spacers and Divot Fill Techniques for Dt-Aligned Processing After Sti Formation for Advanced Deep Trench Capacitor Drams
Patent:
6,331,459 →
Application:
09/252,372 →
System and Method for Automated Defect Inspection of Photomasks
Patent:
6,363,296 →
Application:
09/256,930 →
Extrusion Enhanced Mask for Improving Window
Patent:
6,114,074 →
Application:
09/266,473 →
Cmp Uniformity
Skew Pointer Generation
Patent:
6,367,027 →
Application:
09/273,842 →
Semiconductor Structures and Manufacturing Methods
Patent:
6,245,629 →
Application:
09/276,027 →
Stacked Capacitor Memory Cell and Method of Manufacutre
Patent:
6,083,788 →
Application:
09/277,669 →
In-Situ Method for Preparing and Highlighting of Defects for Failure Analysis
Patent:
6,162,735 →
Application:
09/277,673 →
Method for Reducing Corner Rounding in Mask Fabrication Utilizing Elliptical Energy Beam
Patent:
6,214,496 →
Application:
09/280,615 →
Pulse Width Detection
Patent:
6,324,125 →
Application:
09/281,020 →
Method of Improving the Etch Resistance of Chemically Amplified Photoresists by Introducing Silicon After Patterning
Patent:
6,379,869 →
Application:
09/282,745 →
Improved Top Layer Imaging Lithography for Semiconductor Processing
Patent:
6,316,168 →
Application:
09/290,319 →
Yield Prediction and Statistical Process Control Using Predicted Defect Related Yield Loss
Patent:
6,496,958 →
Application:
09/299,979 →
Static Random Access Memory (Sram)
Patent:
6,472,767 →
Application:
09/302,757 →
Double Gated Transistor
Patent:
6,459,123 →
Application:
09/302,768 →
On Chip Programmable Data Pattern Generator for Semiconductor Memories
Patent:
6,651,203 →
Application:
09/312,974 →
On Chip Data Comparator with Variable Data and Compare Result Compression
Patent:
6,357,027 →
Application:
09/313,016 →
Differential Trench Open Process
Patent:
6,207,573 →
Application:
09/314,358 →
Sensing of Memory Cell via a Plateline
Patent:
6,201,730 →
Application:
09/323,363 →
Low Temperature Sacrificial Oxide Formation
Patent:
6,309,983 →
Application:
09/324,926 →
Low Temperature Self-Aligned Collar Formation
Patent:
6,352,893 →
Application:
09/324,927 →
Layout and Wiring Scheme for Memory Cells with Vertical Transistors
Patent:
6,218,696 →
Application:
09/326,889 →
Low Temperfature Oxidation of Conductive Layers for Semiconductor Fabrication
Patent:
6,387,771 →
Application:
09/327,711 →
Method for Expanding Trenches by an Anisotropic Wet Etch
Device Performance by Employing an Improved Method for Forming Halo Implants
Patent:
6,194,278 →
Application:
09/337,168 →
Semiconductor Manufacturing Methods
Patent:
6,368,516 →
Application:
09/339,519 →
Method for Fabricating 4F2 Memory Cells with Improved Gate Conductor Structure
Patent:
6,355,520 →
Application:
09/374,537 →
Method for Fabrication of Enlarged Stacked Capacitors Using Isotropic Etching
Patent:
6,294,436 →
Application:
09/374,538 →
Sidewall Oxide Process for Improved Shallow Junction Formation in Support Region
Patent:
6,352,934 →
Application:
09/383,666 →
Process for Improving the Thickness Uniformity of a Thin Layer in Semiconcuctor Wafer Fabrication
Patent:
6,235,651 →
Application:
09/395,952 →
Reducing Impact of Coupling Noise in Multi-Level Bieline Architecture
Patent:
6,327,170 →
Application:
09/406,890 →
Reduced Impact from Coupling Noise in Diagonal Bitline Architectures
Patent:
6,320,780 →
Application:
09/406,892 →
Semiconductor Structures and Manufacturing Methods
Patent:
6,590,657 →
Application:
09/408,246 →
Locally Folded Split Level Bitline Wiring
Patent:
6,291,335 →
Application:
09/411,551 →
Spacer Process to Eliminate Corner Transistor Device
Patent:
6,207,513 →
Application:
09/432,063 →
Efficient Redundancy Calculation System and Method for Various Types of Memory Devices
Patent:
6,725,403 →
Application:
09/432,064 →
Memory Cell
Patent:
6,285,619 →
Application:
09/442,982 →
Advanced Bit Fail Map Compression with Fail Signature Analysis
Patent:
6,564,346 →
Application:
09/455,855 →
Self-Aligned Ldd Formation with One-Step Implantation for Transistor Formation
Patent:
6,362,033 →
Application:
09/460,318 →
Automated Creation of Specific Test Programs from Complex Test Programs
Patent:
6,434,503 →
Application:
09/476,449 →
Usage of Redundancy Data for Displaying Failure Bit Maps for Semiconductor Devices
Patent:
6,499,120 →
Application:
09/476,450 →
Method for Making an Anti-Fuse
Patent:
6,335,228 →
Application:
09/476,726 →
Memory Cell for Plateline Sensing
Patent:
6,593,613 →
Application:
09/525,093 →
Process for Improving the Thickness Uniformity of a Thin Oxide Layer in Semiconductor Wafer Fabrication
Patent:
6,537,926 →
Application:
09/638,309 →
Cmp Uniformity
Patent:
6,685,796 →
Application:
09/639,986 →
Double Gated Transistor
Patent:
6,503,784 →
Application:
09/670,742 →
Pulse Width Detection
Patent:
6,400,650 →
Application:
09/687,883 →
Semiconductor Structures and Manufacturing Methods
Semiconductor Structures and Manufacturing Methods
Method for operating a current sense amplifier
Dicing Configuration for Separating a Semiconductor Component from a Semiconductor Wafer
Configuration for Testing Chips Using a Printed Circuit Board
Circuit Configuration for an Integrated Semiconductor Memory with Column Access
Method for Fabricating a Patterned Metal-Oxide-Containing Layer
Integrated semiconductor memory with a memory unit for storing addresses of defective memory cells
Circuit Configuration for Regulating the Power Consumption of an Integrated Circuit
Method for Producing Trenches for Dram Cell Configurations
Method of Producing Alignment Marks
Pulse Generator for Generating an Output in Response to a Delay Time
Circuit Configuration for Measuring the Capacitance of Structures in an Integrated Circuit
Integrated Circuit with a Differential Amplifier
Circuit Configuration Having a Variable Number of Data Outputs and Device for Reading Out Data from the Circuit Configuration with the Variable Number of Data Outputs
Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating mode
Semiconductor Memory Configuration with a Refresh Logic Circuit, and Method of Refreshing a Memory Content of the Semiconductor Memory Configuration
Reactor for Manufacturing a Semiconductor Device
Method and Device for Testing Electronic Components
Electrical Circuit and Method for Testing a Circuit Component of the Electrical Circuit
Method of Testing a Memory Cell Having a Floating Gate
Circuit configuration for generating an output clock signal with optimized signal generation time
Memory component with short access time
Method and circuit configuration for read-write mode control of a synchronous memory
Method for Testing the Refresh Device of an Information Memory
Integrated semiconductor memory
Method and Device for Adapting/Tuning Signal Transit Times on Line Systems or Networks Between Integrated Circuits
Integrated Semiconductor Memory Having Memory Cells with a Ferroelectric Memory Property
Circuit Configuration for Adjusting Signal Delay Times
Integrated semiconductor memory with redundant units for memory cells
Configuration for Generating Signal Impulses of Defined Lengths in a Module with a Bist-Function
Method of Manufacture of a Capacitor with a Dielectric on the Basis of Strontium-Bismuth-Tantalum
Fusible Link Configuration in Integrated Circuits
Fuse Configuration for a Semiconductor Apparatus
Decoding Apparatus
Method and Apparatus for Testing an Sdram Memory Used as the Main Memory in a Personal Computer
Integrated Memory with Plate Line Segments
Redundancy Multiplexer for a Semiconductor Memory Configuration
Method for Filling Depressions in a Surface of a Semiconductor Structure, and a Semiconductor Structure Filled in This Way
Method of Manufacturing a Ferroelectric Capacitor Configuration
Method for fabricating a semiconductor component
Test Structure in an Integrated Semiconductor
Read/Write Amplifier Having Vertical Transistors for a Dram Memory
Method for Regenerating Semiconductor Wafers
Read Amplifier Subcircuit for a Dram Memory
Integrated Dram Memory Cell and Dram Memory
Method for Determining the Temperature of a Semiconductor Chip and Semiconductor Chip with Temperature Measuring Configuration
Redundant Multiplexer for a Semiconductor Memory Configuration
Apparatus for Applying a Semiconductor Chip to a Carrier Element with a Compensating Layer
Method for Carrying Out a Burn-in Process for Electrically Stressing a Semiconductor Memory
Electronic Device Having a Multiplicity of Contact Bumps
Device for Packaging Electronic Components
System Carrier for a Semiconductor Chip Having a Lead Frame
Patent:
6,563,201 →
Application:
09/816,930 →
Semiconductor Component with Method for Manufacturing
Cmos Voltage Divider
Integrated circuit with actuation circuit for actuating a driver circuit
Method for the Metalization of an Insulator and/or a Dielectric
Component Having at Least Two Mutually Adjacent Insulating Layers and Corresponding Production Method
Semiconductor Memory Having a Memory Cell Array
Integrated memory and method for checking the operation of memory cells in an integrated memory
Test Configuration for the Functional Testing of a Semiconductor Chip
Method of Producing Masks for Fabricating Semiconductor Structures
Housing for Semiconductor Chips
Configuration for the Execution of a Plasma Based Sputter Process
Integrated Semiconductor Circuit, in Particular a Semiconductor Memory Configuration, and Method for Its Operation
Circuit Configuration for Reading a Memory Cell Having a Ferroelectric Capacitor
Refresh Drive Circuit for a Dram
Ciruit Configuration with Protection Device
Layout of a Sense Amplifier with Accelerated Signal Evaluation
Field-Effect Transistor Structure with an Insulated Gate
Configuration of a Plurality of Circuit Modules
Integrated Memory with Row Access Control to Activate and Precharge Row Lines, and Method of Operating Such a Memory
Circuit Configuration for Compensating Runtime and Pulse-Duty-Factor Differences Between Two Input Signals
Method for testing a multiplicity of word lines of a semiconductor memory configuration
Fuse Circuit Configuration
Semiconductor Circuit Configuration
Semiconductor Configuration Having an Optical Fuse
Read/Write Amplifier for a Dram Memory Cell, and Dram Memory
Installation for Processing Wafers
Configuration in Which Wafers Are Individually Supplied to Fabrication Units and Measuring Units Located in a Fabrication Cell
Method and Apparatus for Processing Defect Addresses
Light Curtain System for Establishing a Protective Light Curtain, Tool and System for Processing Objects and Method for Loading/Unloading a Tool
Electronic Component Comprising an Electrically Conductive Connection Consisting of Carbon Nanotubes and a Method for Producing the Same
Method for Producing a Ferroelectric Layer
Leadframe Interposer
Fin Field-Effect Transistor and Method for the Production Thereof
Process for Planarization and Recess Etching of Integrated Circuits
Digital Memory Circuit and Method of Manufacturing the Circuit
Semiconductor Component and Method for Its Production
Method and Apparatus for Connecting at Least One Chip to an External Wiring Configuration
Field Effect Transistor and Method for Producing a Field Effect Transistor
Electronic Component with Flexible Contacting Pads and Method for Producing the Electronic Component
Device for Fixing a Heat Distribution Covering on a Printed Circuit Board and Circuit Board with Heat Distribution Covering
Configuration for the Transmission of Signals Between a Data Processing Device and a Functional Unit
Apparatus and Method for Handling, Storing and Reloading Carriers for Disk-Shaped Items, Such as Semiconductor Wafers or Cds
Method for Applying a Semiconductor Chip to a Carrier Element
Electronic Component with Flexible Contacting Pads and Method for Producing the Electronic Component
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 023774/0399 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES RICHMOND, LP
To: QIMONDA AG
Reel/Frame 023792/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Jan 14, 2010
From: INFINEON TECHNOLOGIES CORPORATION
To: QIMONDA AG
Reel/Frame 023848/0326 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Change of Name
Jul 24, 2015
From: SIEMENS MICROELECTRONICS, INC.
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 036180/0539 →
Assignment of Assignor's Interest
Jul 24, 2015
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 036169/0821 →