IP Library Granted Patent US 7,008,493
Granted Patent B2
US 7,008,493 · App. 10/685,065 · Granted Mar 7, 2006

Method for applying a semiconductor chip to a carrier element

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Quick Facts
Patent No.
US 7,008,493
App. No.
10/685,065
Granted
Mar 7, 2006
Kind
B2
Abstract

A method is described for applying an integrated circuit to a carrier element. In which a curable compensating layer of initially paste-like consistency is coated substantially with full coverage onto a lower contact area of the integrated circuit. Whereupon the integrated circuit is joined together, by the compensating layer, with the carrier element after a relative alignment in order then to produce an electrical connection between the integrated circuit and conductor tracks of the carrier element via electrical lines surmounting the thickness of the compensating layer. Whereupon the compensating layer is cured resulting in an increased volume of the compensating layer.

Claims (13)

1. A method for applying a first device to a second device, which comprises the steps of:

providing an integrated circuit having a lower contact area;

providing a carrier element having conductor tracks;

coating a curable compensating layer having an initially pasty consistency substantially with full coverage onto one of the lower contact area of the integrated circuit and onto the carrier element;

subsequently joining the integrated circuit in an adhering manner, due to the curable compensating layer, to the carrier element after relative alignment;

producing an electrical connection between the integrated circuit and the conductor tracks of the carrier element via electrical lines surmounting a thickness of the curable compensating layer; and

curing the curable compensating layer resulting in an increased volume of the curable compensating layer.

2. The method according to claim 1 , which comprises fastening the electrical lines in an untautened manner between the integrated circuit and the carrier element, so that the electrical lines are tautened during an increase in the volume of the curable compensating layer.

3. The method according to claim 1 , which comprises increasing the volume of the curable compensating layer by introducing a gas during one of the coating step and the curing step.

4. The method according to claim 1 , which comprises increasing the volume of the curable compensating layer by a substance which liberates gas during the curing process and is admixed with a material forming the curable compensating layer.

5. The method according to claim 1 , which comprises increasing a temperature of the curable compensating layer for assisting in the curing step.

6. The method according to claim 1 , which comprises irradiating the curable compensating layer with ultraviolet light during the curing step.

7. The method according to claim 2 , which comprises fastening the electrical lines using a bonding method.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036539/0196 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →