IP Library Granted Patent US 6,977,413
Granted Patent B2
US 6,977,413 · App. 10/220,344 · Granted Dec 20, 2005

Bar-type field effect transistor and method for the production thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,977,413
App. No.
10/220,344
Granted
Dec 20, 2005
Kind
B2
Abstract

The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

Claims (14)

1. A fin field-effect transistor, comprising:

a substrate;

a fin above the substrate, the fin comprising a source region, a channel region and a drain region;

a gate oxide formed along side walls of the fin and above the fin; and

a gate and a spacer above the channel region of the fin, wherein the spacer is formed on side walls of the gate and separately from the gate oxide, wherein the side walls of the fin in the source region and in the drain region are uncovered from the spacer for implantation of the source region and the drain region of the fin with doping atoms.

2. The fin field-effect transistor as claimed in claim 1 , in which the gate and the spacer extend essentially along the entire height of the part of the fin.

3. The fin field-effect transistor as claimed in claim 1 , in which the substrate has a layer of silicon oxide provided above the substrate.

4. The fin field-effect transistor as claimed in claim 1 , in which the fin has silicon.

5. The fin field-effect transistor as claimed in claim 1 , in which the gate has polysilicon.

6. The fin field-effect transistor as claimed in claim 1 , in which the spacer comprises silicon oxide and/or silicon nitride.

7. The fin field-effect transistor as claimed in claim 1 , in which the spacer has a first spacer part with silicon oxide and a second spacer part with silicon nitride, the second spacer part being arranged above the first spacer part.

8. The fin field-effect transistor as claimed in claim 1 , in which an etching stop layer is provided between the substrate and the fin and the gate.

9. The fin field-effect transistor as claimed in claim 8 , in which the etching stop layer has silicon nitride.

10. The fin field-effect transistor as claimed in claim 1 , in which the height of the spacer with respect to the substrate is essentially equal to the height of the gate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036539/0196 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →