IP Library › Granted Patent US 6,459,631
Granted Patent Utility
US 6,459,631 · Confirmation No. 7635

CONFIGURATION FOR IMPLEMENTING REDUNDANCY FOR A MEMORY CHIP

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 Code Description Pages PDF
2001-07-18 TRNA Transmittal of New Application 1 View
2001-07-18 SPEC Specification 11 View
2001-07-18 CLM Claims 5 View
2001-07-18 ABST Abstract 1 View
2001-07-18 DRW Drawings-only black and white line drawings 3 View
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Quick Facts
Patent No.
US 6,459,631
App. No.
09/907,783
Filed
2001-07-18
Granted
2002-10-01
Pub. No.
US20020012281A1
Art Unit
2818
PTA
-100 days