Patent Assignment
Reel/Frame 023853/0401
Assignment of Assignor's Interest
Recorded: 2010-01-14
Pages: 388
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties
(89)
Metal Interconnect Structure for an Integrated Circuit with Improved Electromigration Reliability
Patent:
5,641,992 →
Application:
08/513,494 →
Non-Destructive Method and Device for Measuring the Depth of a Buried Interface
Patent:
6,124,141 →
Application:
09/004,074 →
Dummy Patterns for Aluminum Chemical Polishing (Cmp)
Patent:
6,093,631 →
Application:
09/007,911 →
Reduced Voltage Input/Reduced Voltage Output Tri-State Buffers
Patent:
6,181,165 →
Application:
09/037,289 →
Recovery of Electronic Properties in Hydrogen-Damaged Ferroelectrics by Low-Temperature Annealing in an Inert Gas
Quantum Conductive Recrystallization Barrier Layers
Patent:
6,194,736 →
Application:
09/213,674 →
Crack Stop Between Neighboring Fuses for Protection from Fuse Blow Damage
Patent:
6,486,526 →
Application:
09/223,826 →
Vertical Fuse and Method of Fabrication
Patent:
6,242,789 →
Application:
09/255,767 →
Metal Wire Fuse Structure with Cavity
Patent:
6,268,638 →
Application:
09/258,563 →
Method and Apparatus for the Replacement of Non-Operational Metal Lines in Drams
Patent:
6,259,309 →
Application:
09/305,434 →
Hybrid 5F2 Cell Layout for Buried Surface Strap Aligned to Vertical Transistor
Patent:
6,229,173 →
Application:
09/339,271 →
Tungsten Hard Mask for Dry Etching Aluminum-Containing Layers
Patent:
6,420,099 →
Application:
09/366,132 →
Dynamic Random Access Memory Cell Layout
Patent:
6,118,683 →
Application:
09/407,437 →
Center Node for Deep Trench Capacitors
Patent:
6,271,557 →
Application:
09/412,481 →
Self-Aligned Metal Caps for Interlevel Metal Connections
Patent:
6,261,950 →
Application:
09/420,402 →
Dummy Feature Reduction Using Optical Proximity Effect Correction
Patent:
6,426,269 →
Application:
09/422,634 →
Optimized Decoupling Capacitor Using Lithographic Dummy Filler
Patent:
6,232,154 →
Application:
09/442,890 →
Process for Fabricating a Uniform Gate Oxide of a Vertical Transistor
Patent:
6,150,670 →
Application:
09/450,546 →
Sdram with a Maskable Input
Patent:
6,240,043 →
Application:
09/456,588 →
Prefetch Write Driver for a Random Access Memory
Patent:
6,292,402 →
Application:
09/456,589 →
High Performance Cmos Word-Line Driver
Patent:
6,236,617 →
Application:
09/458,878 →
Semiconductor Device Fabrication Using a Photomask with Assist Features
Patent:
6,421,820 →
Application:
09/460,034 →
Method for Removal of Hard Mask Used to Define Noble Metal Electrode
Patent:
6,420,272 →
Application:
09/460,700 →
Semiconductor Structure and Manufacturing Methods
Patent:
6,319,788 →
Application:
09/460,701 →
Charge Pump System Having Multiple Independently Activated Charge Pumps and Corresponding Method
Patent:
6,275,096 →
Application:
09/460,820 →
Cvd/Pvd/Cvd/Pvd Fill Process
Patent:
6,361,880 →
Application:
09/469,371 →
Slurry-less chemical-mechanical polishing of oxide materials
Patent:
6,358,850 →
Application:
09/471,428 →
Maskless process for self-aligned contacts
Patent:
6,261,924 →
Application:
09/489,865 →
Full swing voltage input/full swing output bi-directional repeaters for high resistance or high capacitance bi-directional signal lines and methods therefor
Patent:
6,313,663 →
Application:
09/491,635 →
Overlay Alignment System Using Polarization Schemes
Patent:
6,525,818 →
Application:
09/500,110 →
Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates
Patent:
6,362,040 →
Application:
09/501,502 →
Method for probing semiconductor devices for active measuring of electrical characteristics
Patent:
6,288,558 →
Application:
09/504,409 →
Method for addressing electrical fuses
Patent:
6,166,981 →
Application:
09/512,922 →
Method of Using Optical Proximity Effects to Create Electrically Blown Fuses with Sub-Critical Dimension Neck Downs
Patent:
6,436,585 →
Application:
09/512,923 →
Receiver with switched current feedback for controlled hysteresis
Patent:
6,275,082 →
Application:
09/519,104 →
Fuse Processing Using Dielectric Planarization Pillars
Patent:
6,420,216 →
Application:
09/525,729 →
Semiconductor Contact and Method of Forming the Same
Patent:
6,486,505 →
Application:
09/535,445 →
Method for Forming an Integrated Barrier/Plug for a Stacked Capacitor
Patent:
6,420,267 →
Application:
09/551,757 →
Semiconductor Memory Device with Reduced Orientation-Dependent Oxidation in Trench Structures
Patent:
6,437,381 →
Application:
09/560,081 →
Multiple Exposure Process for Formation of Dense Rectangular Arrays
Patent:
6,511,791 →
Application:
09/561,469 →
Plural Interleaved Exposure Process for Increased Feature Aspect Ratio in Dense Arrays
Patent:
6,451,508 →
Application:
09/561,472 →
Capacitor stack structure and method of fabricating description
Patent:
6,339,007 →
Application:
09/562,556 →
Semiconductor memory with programmable bitline multiplexers
Patent:
6,272,062 →
Application:
09/583,596 →
Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow
Patent:
6,348,395 →
Application:
09/589,818 →
Clean method for recessed conductive barriers
Patent:
6,358,855 →
Application:
09/595,795 →
Orientation independent oxidation of silicon
Patent:
6,358,867 →
Application:
09/596,097 →
Power Controlled Input Receiver
Patent:
6,462,613 →
Application:
09/597,121 →
Removable Inorganic Anti-Reflection Coating Process
Patent:
6,607,984 →
Application:
09/597,122 →
Method of Reducing Post-Development Defects in and Around Openings Formed in Photoresist by Use of Multiple Development/Rinse Cycles
Patent:
6,372,408 →
Application:
09/598,374 →
Buried bit line-field isolation defined active semiconductor areas
Patent:
6,911,687 →
Application:
09/598,789 →
Structure and process for 6F2 trench capacitor dram cell with vertical mosfet and 3F bitline pitch
Patent:
6,339,241 →
Application:
09/602,426 →
Single Sided Buried Strap
Patent:
6,573,137 →
Application:
09/603,442 →
Highly Conformal Titanium Nitride Deposition Process for High Aspect Ratio Structures
Patent:
6,399,490 →
Application:
09/607,131 →
Disposable Spacer Technology for Device Tailoring
Patent:
6,444,531 →
Application:
09/645,424 →
Semiconductor Structure and Method of Fabrication Including Forming Aluminum Columns
Patent:
6,635,564 →
Application:
09/662,424 →
Process for Protecting Array Top Oxide
Patent:
6,509,226 →
Application:
09/670,741 →
Method to Descramble the Data Mapping in Memory Circuits
Patent:
6,601,205 →
Application:
09/675,953 →
Metal Wire Fuse Structure with Cavity
Method for the Determination of Resistances and Capacitances of a Circuit Diagram, Which Represents an Electrical Circuit
Vertical Mosfet with Asymmetrically Graded Channel Doping
Patent:
6,573,561 →
Application:
10/096,192 →
Method to Increase the Etch Rate and Depth in High Aspect Ratio Structure
Plasma-Etching Process for Molybdenum Silicon Nitride Layers on Half-Tone Phase Masks Based on Gas Mixtures Containing Monofluoromethane and Oxygen
Method for Fabricating Positionally Exact Surface-Wide Membrane Masks
Non-Volatile Memory Cell and Fabrication Method
Method of Producing a Perforated Mask for Particle Radiation
Insulating Cap Layer and Conductive Cap Layer for Semiconductor Devices with Magnetic Material Layers
Etching Processing Method for a Material Layer
Large-Area Membrane Mask and Method for Fabricating the Mask
Method for Etching High-Aspect-Ratio Features
Particle Measurement Configuration and Semiconductor Wafer Processing Device with Such a Configuration
Configuration for Determining a Concentration of Contaminating Particles in a Loading and Unloading Chamber of an Appliance for Processing at Least One Disk-Like Object
Error Detection and Correction Method and Apparatus in a Magnetoresistive Random Access Memory
Patent:
6,704,230 →
Application:
10/250,201 →
Spacer Integration Scheme in Mram Technology
Method for Fabricating a Trench Capacitor
Bilayer Cmp Process to Improve Surface Roughness of Magnetic Stack in Mram Technology
Silicon Nitride Island Formation for Increased Capacitance
Wordline on and Off Voltage Compensation Circuit Based on the Array Device Threshold Voltage
Patent:
6,693,843 →
Application:
10/318,795 →
Internal data generation and compare via unused external pins
Application:
10/336,140 →
Publication:
US 2004/0133827
High Density Plasma Oxidation
Apparatus and Method to Improve Resist Line Roughness in Semiconductor Wafer Processing
Gate Metal Recess for Oxidation Protection and Parasitic Capacitance Reduction
Nozzle Assembly for Applying a Liquid to a Substrate
Hdp Process for High Aspect Ratio Gap Filling
Magnetically Lined Conductors
Method for Formong Itto Nitride Liner for Improved Collar Protection and Tto Reliability
Method for Generating Chip Stacks
Photoresist Suitable for Use in 157 Nm Photolithography and Including a Polymer Based on Fluorinated Norbornene Derivatives
Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell
Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Assignment of Assignor's Interest
Dec 7, 2015
From: INFINEON TECHNOLOGIES AG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037221/0885 →