Spacer integration scheme in MRAM technology
View Patent ↗A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
1. A method of making at least one magnetic memory cell comprising the steps of:
depositing a memory stack of magnetic materials containing a pinned layer, a free layer and a tunnel barrier layer disposed between said pinned layer and said tunnel layer;
forming an etch-resistant mandrel defining at least one cell area of said memory stack;
patterning at least one layer of said memory stack by etching outside said mandrel, leaving an exposed vertical surface of said at least one layer;
forming substantially vertical protective sidewalls about said memory stack, covering said exposed vertical surface; and
patterning at least one remaining layers of said memory stack, whereby said exposed vertical surface is protected during said step of patterning said remaining layers of said memory stack.
2. A method according to claim 1 , in which said free layer is the top layer of said memory stack and said step of patterning comprises etching through said free layer and stopping the etch on said tunnel barrier layer.
3. A method according to claim 1 , in which said free layer is the top layer of said memory stack and said step of patterning comprises etching through said free layer and said tunnel barrier layer and stopping the etch on said pinned layer.
4. A method according to claim 3 , in which said free layer is the top layer of said memory stack and said step of patterning comprises etching through said free layer and said tunnel barrier layer and stopping the etch in a pinning layer that is a sublayer of a composite pinned layer.
5. A method according to claim 1 , further comprising a step of depositing a conformal dielectric over said mandrel and etching said conformal dielectric directionally to form said protective sidewalls extending over edges of said free layer and tunnel barrier layer exposed by said step of etching.
6. A method according to claim 5 , further comprising a step of etching through said pinned layer outside said sidewalls, whereby a pinned layer of said memory cell is formed that extends underneath said sidewalls and is self-aligned with said free layer and tunnel barrier layer and whereby exposed edges of said free layer and said tunnel barrier layer are protected from deposition of sputtered material during the etching process.
7. A method According to claim 6 , further comprising a step of depositing an interlayer dielectric around said mandrel, thereby enclosing said sidewalls, up to a top level of said mandrel;
removing said mandrel, exposing a top layer of said magnetic stack at the bottom of a mandrel aperture; and
depositing a conductive material in said mandrel aperture, thereby forming a cell contact.
8. A method according to claim 2 , further comprising a step of depositing a conformal dielectric over said mandrel and etching said conformal dielectric directionally to form said protective sidewalls extending over edges of said free layer and tunnel barrier layer exposed by said step of etching.
9. A method according to claim 8 , further comprising a step of etching through said pinned layer outside said sidewalls, whereby a pinned layer of said memory cell is formed that extends underneath said sidewalls and is self-aligned with said free layer and tunnel barrier layer and whereby exposed edges of said free layer and said tunnel barrier layer are protected from deposition of sputtered material during the etching process.
10. A method according to claim 9 , further comprising a step of depositing an interlayer dielectric around said mandrel, thereby enclosing said sidewalls, up to a top level of said mandrel;
removing said mandrel, exposing a top layer of said magnetic stack at the bottom of a mandrel aperture; and
depositing a conductive material in said mandrel aperture, thereby forming a cell contact.